全文获取类型
收费全文 | 227篇 |
免费 | 20篇 |
国内免费 | 6篇 |
专业分类
电工技术 | 3篇 |
综合类 | 13篇 |
化学工业 | 8篇 |
金属工艺 | 4篇 |
机械仪表 | 4篇 |
建筑科学 | 2篇 |
能源动力 | 1篇 |
轻工业 | 4篇 |
武器工业 | 1篇 |
无线电 | 108篇 |
一般工业技术 | 6篇 |
冶金工业 | 5篇 |
自动化技术 | 94篇 |
出版年
2022年 | 2篇 |
2021年 | 3篇 |
2019年 | 2篇 |
2016年 | 2篇 |
2015年 | 4篇 |
2014年 | 3篇 |
2013年 | 3篇 |
2012年 | 3篇 |
2011年 | 5篇 |
2010年 | 4篇 |
2009年 | 11篇 |
2008年 | 10篇 |
2007年 | 19篇 |
2006年 | 14篇 |
2005年 | 20篇 |
2004年 | 22篇 |
2003年 | 36篇 |
2002年 | 36篇 |
2001年 | 12篇 |
2000年 | 25篇 |
1999年 | 9篇 |
1998年 | 5篇 |
1997年 | 3篇 |
排序方式: 共有253条查询结果,搜索用时 0 毫秒
201.
202.
1 IntroductionH .2 63standard[1 ] isablock basedvideocodingschemeanddesignedforlowbit rateapplications.MEisakeycomponentintheH .2 63encode 相似文献
203.
204.
A compressed video bitstream is sensitive to errors that may severely degrade the reconstructed images even when the bit error rate is small. One approach to combat the impact of such errors is the use of error concealment at the decoder without increasing the bit rate or changing the encoder. For spatial‐error concealment, we propose a method featuring edge continuity and texture preservation as well as low computation to reconstruct more visually acceptable images. Aiming at temporal error concealment, we propose a two‐step algorithm based on block matching principles in which the assumption of smooth and uniform motion for some adjacent blocks is adopted. As simulation results show, the proposed spatial and temporal methods provide better reconstruction quality for damaged images than other methods. 相似文献
205.
叙述一种采用DSP实现H.263标准规定的码流复合部分的方法。为了达到实时性的要求,对VLC码表的查表方法和DSP汇编程序进行了优化。所提出的码流复合优化方法已在H.263标准的硬件系统中实现。并且准备应用于MPEG-4标准的硬件系统中。 相似文献
206.
1 IntroductionWiththerapidlydevelopmentofmultimediacommunicationtechnology ,theH .2 6 1 ,MPEG 1andMPEG 2recommendationshavebeenestab lishedbytherelevantorganizationsofITU TorISOinthepastyears.Thesestandardsprovidethetoolsforimagestoreortransmissionatthehigher… 相似文献
207.
208.
Scalable Parallel Memory Architectures for Video Coding 总被引:1,自引:0,他引:1
Current video compression standards, which process frames macroblock by macroblock, employ several processing functions to achieve the compression. These functions refer to data memory address space in different ways. E.g., performing motion estimation and motion compensation functions requires many times data accesses unaligned to word boundaries. On the other hand, Discrete Cosine Transformation (DCT) and inverse of it (IDCT) for 8 × 8 block can be performed first for rows and then for columns. Thus, transposition is needed between these two stages. Among other things, parallel memory architecture can provide a solution for these tasks. In our other paper, we shortly surveyed parallel memory architectures and proposed parallel memory architecture designs for different data path widths for video coding applications. In this paper, we construct video coding function examples by using the proposed parallel data memory efficiently. Furthermore, performance and implementation cost of the parallel memory architecture are estimated and compared to more conventional memory architectures. The examples are given for different data bus widths (16, 32, 64, and 128 bits). We show that the parallel memory can keep the data path fully utilized in many video coding function implementations. This ensures high-speed operation and full utilization of the processing resources. 相似文献
209.
210.