基于H.263的实时视频编码技术研究

为了提高H．263编码技术现有算法的执行效率，本文提出了一种基于时域预测的预判零方法，该方法在保证一定图像质量的条件下具有较高的判别效率，能节约大量的编码时间：并在此基础上结合“钻石”运动搜索算法、MMX优化技术，实现了利用软件进行实时视频编码。     

基于TMS320C6211的实时视频编码器

介绍了一种以TMS320621为核心处理器的实时视频编码器，它采用ITU-T的H.263压缩标准，可以满足当前远程视频监控、会议电视等诸多视频/图像处理和传输领域的需求。同时，对编码器的硬件资源选择、系统工程流程、视频采集、软件开发等关键技术作了详细讨论。最后，分析了该编码器的实时性能和其它性能。     

基于H.263视频压缩的新钻石搜索算法

提出了一种基于H．263的改进的新钻石搜索算法。给出了算法流程图，重点对根据该算法自行编写并检验通过的精华程序段进行了详细的介绍和讨论。仿真实验的结果证明，实际编程实现的新钻石搜索算法远远胜于传统三步搜索法，从而大大提高了计算速度和压缩率。     

基于H.263标准的视频压缩算法的优化及研发

介绍了基于H．263标准的视频压缩算法，对作为视频压缩关键技术的运动估计算法进行了深入的研究，提出了一种改进算法，并引入英特尔公司的MMX技术进行双重优化后的新钻石搜索算法，以消除原钻石搜索算法中大量的重复计算。仿真实验结果证明，双重优化的新算法大大地提高了计算速度和压缩率。相应的研发成果已在本课题组与烟台正达公司的合作项目中得到了应用，并通过了验收，取得了令人满意的效果。     

基于DSP的H.263视频压缩处理信息存取策略研究

结合Ti公司的TMS320C6711DSP的结构特点和ITU-TH．263视频压缩标准的实时性要求，研究了H．263视频压缩编码程序和数据的存取策略，提出实现方案。     

On Design of Parallel Memory Access Schemes for Video Coding

Some of the modern powerful digital signal processors (DSPs) have byte-addressable internal data memory. This property is valuable especially in computationally demanding inter frame video encoding, where data accesses are typically unaligned according to word boundaries. The byte-addressable memory allows load or store command to start accessing from any byte-address, providing at most as many successive bytes from subsequent addresses as data bus can handle in parallel. Maybe the simplest way to construct such a byte-addressable memory is to use N 8-bit memory modules or banks to be accessed in parallel, when N is data bus width in bytes. However, in addition to byte-addressable subsequent bytes, memory consisting of parallel memory modules can provide much more versatile addressing capabilities with reasonable implementation cost. Versatile access formats can significantly reduce the need for data reordering in the register file. At first, we provide motivation for using parallel memory architecture with versatile access formats as an internal on-chip data memory of modern DSP. After this, notations are described and general view of parallel memory design is given. We propose some example parallel data memory architecture designs with data access formats especially helpful in H.263 encoding and MPEG-4 core profile motion and texture encoding. The examples are given for different data bus widths (16, 32, 64, and 128 bits). Finally, performance is shortly compared to other memory architectures and area, delay, and power figures are estimated.Jarno K. Tanskanen was born in Joensuu, Finland in 1975. He studied analog and digital electronics in the Department of Electrical Engineering, and computer architecture in the Department of Information Technology at Tampere University of Technology, where he received his M.Sc. degree in 1999. He is currently working as a research scientist in the Institute of Digital and Computer Systems at TUT. His Dr.Tech. research concerns parallel processing of video compression. jarno.tanskanen@tut.fiReiner Creutzburg received his Diploma in Mathematics in 1976 and attained his Ph.D. in Mathematics in 1984 from the Rostock University, Germany. Prof. Creutzburg has published 3 books, filed 2 patents, and produced approximately 100 articles, preprint, and conference papers. Professional Experience: Since 2000—Part-time Professor for Multimedia technology, Tampere University of Technology, Finland. Since 1992—Full-time Professor of Computer Science, Fachhochschule Brandenburg-University of Applied Sciences, Brandenburg, Germany. 1990 to 1992—Assistant Professor, University of Karlsruhe, Institute of Algorithms and Cognitive Systems, Germany. 1987 to 1989—Head of the Research Section Image Processing. 1986 to 1989—Founder and Head of the International Base Laboratory of Image Processing and Computer Graphics for East European countries at the Central Institute of Cybernetics and Information Processes of the Academy of Sciences (Berlin), Germany. 1976 to 1989—Researcher and Assistant Professor in various Universities and the Academy of Sciences, Central Institute of Cybernetics and Information, Berlin. creutzburg@fh-brandenburg.deJarkko T. Niittylahti was born in Orivesi, Finland, in 1962. He received the M.Sc, Lic.Tech, and Dr.Tech degrees at Tampere University of Technology (TUT) in 1988, 1992, and 1995, respectively. From 1987 to 1992, he was a researcher at TUT. In 1992–93, he was a researcher at CERN in Geneva, Switzerland. In 1993–95, he was with Nokia Consumer Electronics, Bochum, Germany, and in 1995–97 with Nokia Research Center, Tampere, Finland. In 1997–2000, he was a Professor at Signal Processing Laboratory, TUT, and in 2000–2002 at Institute of Digital and Computer Systems, TUT. Currently, he is a Docent of Digital Techniques at TUT and the managing director of Staselog Ltd. He is also a co-founder and President of Atostek Ltd. He is interested in designing digital systems and architectures. jarkko.niittylahti@tut.fi     

基于CDMA 1X的无线视频传输系统

设计并实现了基于CDMA 1X的无线视频传输系统,详细论述了传输模块中PPP连接、RTP封装和Socket通信的设计过程.并针对CDMA 1X信道的特点.进行了视频差错控制技术方面的研究,在平衡图像质量和编码比特率这对矛盾方面获得了良好的效果.     

DSP实现H263协议图像压缩编码

根据DSP的特点进行选型,选择了TMS320C6000系列的芯片作为图像压缩的硬件处理平台。利用CCS2．0仿真开发环境,对系统的软件进行了设计和仿真,实现了主要的编码运算和码率控制,并且利用DSP自带函数,根据图像压缩的特点进行了代码的优化,给出了软件总体流程和主要算法的框图,为代码的移植准备了条件。在硬件方面以DSP为核心处理器,设计发了基于DSP的图像处理平台,详细绘出原理电路图。最后将软件代码移植到硬件平台,并且进行了高压缩比的图像编码。探讨了基于DSP实现H263压缩编码的问题,指出了未来努力的方向。     

视频会议系统多画面软件设计与分析

多画面合成是视频会议中的关键技术.文中对视频数据流的捕获、解码及对任意多.个画面合成的原理进行了分析.给出了采用多画面合成技术来设计视频会议系统的具体方案.该方案具有计算复杂度低、处理速度快、延时小且画面质量高等特点.     

一种基于IP的视频监控系统设计

提出了一种基于IP的视频监控系统设计,阐述了视频编码系统的硬件结构体系和实时视频软件解码系统的设计方案,就视频数据网络传输中的数据处理等关键技术进行了分析。