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This paper describes the characteristics of a new CAD tool that enables the creation of layout libraries of selected analog modules. This Analog Modules Generator (AMG) automatically creates multiple layout versions of two commonly used analog structures: the differential pair and arrays of series-connected or stacked devices, for the subsequent generation of layout libraries. Based on the number of devices and rows defined by the user for the layout implementation, the tool validates all possible implementations, which are later saved in a database. Additionally, an extraction process can be optionally executed over all the layout views saved in the database. The AMG generates several reports with all the characteristics of the implemented layouts, including area and parasitic components, facilitating further statistical processing. We describe the features and capabilities of the proposed AMG tool, and several test cases are presented. Results show that suitable layout implementations can be achieved by layout and circuit designers in a very reduced amount of time. 相似文献
83.
为了对煤田地震采空区更好地进行探测,结合以往应用实例,采用时间剖面和能量剖面联合对比解释为主,多属性平面属性解释为辅,并结合其它属性联合分析的方法,对采空区进行解释。结果表明:利用多种方法相结合的解释技术,采空区解释是可行的,具有推广价值。 相似文献
84.
《Measurement》2016
A linear interpolator with compressed output and its alternative version that supports error correction are presented in this paper. The interpolation devices can be driven by an Analog/Digital Converter (ADC) that accepts as input, low frequency signals, like sensor values. The proposed interpolation methods can correct ADC linearity errors and increase the dynamic resolution of an ADC or they can reconstruct a signal from fewer samples in non-uniform distance. If the input signal is partially exponential or logarithmic then, specific correction rules can be employed to achieve a lower signal quantization error. These rules are based on simple operations like shifts and comparisons and thus, they can be implemented using low complexity hardware. Spline, Linear, Quadratic interpolation, popular compression tools and reference signals are used to evaluate the experimental results. The proposed architecture is scalar since multiple interpolators can be connected in series. A 3-stage interpolator with 9-bit input and 12-bit typical output resolution was tested with sinusoidal input. The Signal to Noise and Distortion Ratio (SNDR) of the ADC that has been used was increased up to the double. The proposed method was also tested using a pressure sensor, an acoustic signal and image reconstruction leading to Mean Square Error (MSE) that is up to 10 times lower. The achieved compression ratio, ranges between 11% and 76%. The implementation complexity of a one stage interpolator with 9-bit input resolution requires 583 Logic Elements (LE) i.e., less than 3% of the LEs that exist in an Altera Cyclone III EP3C25N Field Programmable Gate Array (FPGA). 相似文献
85.
提出一种有效的识别方法,解决了Turbo编码类型的盲识别问题。首先,在理论分析Turbo码固有结构的基础上,通过特定的拆分和组合方式从Turbo编码序列中获取一路递归系统卷积码,和二路线性分组码,从而根据此特性利用秩统计的方法实现Turbo码的判别;然后对递归系统卷积码输出数据进行差分运算,推导出差分后结果仅与寄存器中存放的数据有关,因此通过一阶累积量的方法可以准确获取归零状态的位置,从而实现对Turbo码的归零特性判别。仿真结果表明:该方法能够实现对Turbo编码类型的识别,且具有较好的容错性能,最后也验证了该方法在较高误码条件下具有较好的识别效果。 相似文献
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88.
在n-Rayleigh信道下,研究了MRC(Maximal Ratio Combining)合并接收系统的平均码字错误率(ASEP)性能。基于矩生成函数(MGF)的方法,推导了MRC接收系统在n-Rayleigh衰落信道上采用M进制相移键控(MPSK),M进制正交幅度调制(MQAM)和M进制脉冲幅度调制(MPAM)等几种M进制数字调制方式的ASEP的计算式。然后在不同条件下,仿真了系统的ASEP性能,仿真值与理论值相一致,理论分析的正确性得到了证明。分析结果表明:分集支路数和衰弱因子对系统的ASEP性能有重要影响。 相似文献
89.
《Microelectronics Journal》2015,46(8):758-776
This paper presents a new high frequency Regulated Cascode (RGC) amplifier with improved performance. The split-length compensation technique is used to increase both the bandwidth and output impedance, and decrease the input impedance of the conventional RGC. The bandwidth of the proposed RGC amplifier is 5.81 GHz, which is about 2.7 GHz larger than that of simple one. The improved performance of the introduced circuit is achieved with no additional passive element and DC power dissipation. In the paper, output impedance and bandwidth of the proposed circuit are derived by using small signal analysis and have also been compared with the traditional one. In addition, a wideband high performance current mirror is designed in the work as an application of the proposed RGC structure. The bandwidth extension ratio (BWER) of the modified wideband current mirror is 1.37. The proposed circuits are designed by using TSMC 0.18 µm CMOS process and BSIM3 Level 49 device model. The circuits are simulated on Spectre simulator of Cadence to validate the analytical results obtained in the paper. 相似文献
90.