基于尖点突变理论的矿房间矿柱的稳定性分析

为了便于分析,对矿房矿柱系统进行了简化,简化后变为固支梁-矿柱力学系统,同时建立了它们的力学模型。根据力学系统的本构关系,确立了尖点突变理论模型。通过分析表明矿柱失稳只跟矿房矿柱自身的内部条件有关,而与外界的作用无关。同时还研究了矿柱突跳失稳的释能机制,研究表明,失稳所释放的能量也仅跟矿房矿柱系统自身有关。最终得出结论,合理优化矿房矿柱自身系统的力学-几何特性参数,破坏产生矿柱突变失稳的充要条件,是控制矿柱稳定性、保证安全生产的有效手段。     

智能机内测试研究综述

机内测试(BIT)是一种能显著提高系统测试性和诊断能力的重要技术,已大量应用于当代航空系统和武器装备中.但虚警问题是困扰BIT应用的重大难题,并严重影响着武器装备的战备完好性和全寿命周期费用;因此,为从根本上解决BIT的虚警问题,智能BIT技术就成为测试领域21世纪的重点研究项目之一;首先简要介绍了BIT虚警的两个主要产生原因,然后重点概述了智能BIT的发展状况,并分析了当前研究方法中存在的不足,最后在研究BIT不确定性的基础上提出了基于粗糙集的智能BIT故障诊断新技术,并指出了该技术中需要研究的若干关键问题.     

基于扫描森林结构的种子编码方案

扫描森林是一种有效的扫描结构，它能够大幅度地降低测试应用开销、测试功耗以及测试数据容量。该文针对采用扫描森林结构的待测电路提出了一种新的种子编码方案。在该方案中，伪随机测试向量覆盖电路中的易测故障，使用ATPG对剩余故障生成确定性测试向量，将其中某一测试向量对应的种子编码为LFSR扩展成该向量需要运行的时钟周期数。实验结果表明，提出的方案能大幅度地降低种子存储数据量，最大降幅达到了83.3％。     

基于无传感器信息的数控机床导轨水平倾角测量方法研究

基于无传感器信息,结合先进的数据处理技术和特征提取方法对数控机床导轨水平倾角进行测量,实现导轨水平倾角的无传感器测量。与传统的测量装置相比,无传感器信号信噪比更高,不仅能在空载下测量,还可以在机床加工过程中测量。     

Multiple-output parity bit signature for exhaustive testing

In this article we propose a multiple-output parity bit signature generation method for exhaustive testing of VLSI circuits. Given a multiple-output combinational circuit, a parity bit signature is generated by first EXORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. The method preserves all the desirable properties of the conventional single-output circuits response analyzers and can be readily implemented using the current VLSI technology.     

Interface engineering of bi-layer semiconductor SrCoSnO3-δ-CeO2-δ heterojunction electrolyte for boosting the electrochemical performance of low-temperature ceramic fuel cell

A comparative study is performed to investigate the electrochemical performance of the low-temperature ceramic fuel cells (CFCs) utilizing two different novel electrolytes. First, a perovskite semiconductor SrCo_0.3Sn_0.7O_3-δ was used as an electrolyte in CFCs due to its modest ionic conductivity (0.1 S/cm) and demonstrated an acceptable power density of 360 mW/cm² at 520 °C. The performance of the cell was primarily limited due to the moderate ionic transport in the electrolyte. In order to improve the ionic conductivity, a new strategy of using a novel bi-layer electrolyte concept consist of SrCo_0.3Sn_0.7O_3-δ and CeO_2-δ in CFCs. These bi-layers of two electrolytes have successfully established heterojunction which considerably improved the ionic conductivity (0.2 S/cm) and enhance the open-circuit voltage of the cell from 0.98 V to 1.001 V. Moreover, the CFCs utilizing bi-layer electrolyte have produced a remarkable power density of 672 mW/cm² at 520 °C. This enhancement of ionic conduction, power density and blockage of electron conduction in the bi-layer electrolyte was studied via band alignment mechanism based on proposed p-n heterojunction. Our work presents a promising methodology for developing advanced low-temperature CFC electrolytes.     

A Novel BIRA Method with High Repair Efficiency and Small Hardware Overhead

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.     

Proportional BIC sensor for current testing

A new design of a BIC sensor for current testing static CMOS circuits is proposed. It is based on a lateral BJT device which is easy to incorporate in any standard CMOS process. The design diverts a fraction of the I _DDQ current from the cell under test and a resistive component generates a voltage proportional to I _DDQ . Additional features are the possibility of continuous measure of i _dd and increased speed of this sensor compared with sensors based on the current integration principle. The design does not have substrate currents due to the parasitic vertical BJTs. Experimental work on the sensor is reported.     

Functional in-circuit characterisation of ΣΔ modulators

A method for the in-circuit functional testing of ΣΔ modulators is described which can be built in large integrated circuits or systems-on-chip. It allows for measuring gain and phase, as well as total harmonic distortion and signal to noise and harmonic distortion ratio parameters. This method can be built in-circuit using existing computational resources, such as digital signal processors or (re)configurable logic, which can therefore be used to implement both mission and test operations. Both simulation and experimental results were obtained which are in close agreement with those expected from the theory.     

Cyclic code weight spectra and BIST aliasing

In built-in self-test for logic circuits, test data reduction can be achieved using a linear feedback shift register. The probability that this data reduction will allow a faulty circuit to be declared good is the probability of aliasing. Based on the independent bit-error model, we show that the code spectra for the cyclic code generated by the feedback polynomial can be used to obtain an exact expression for the aliasing probability of a multiple input signature register when the test length is a multiple of the cycle length. Several cases are examined and, as expected, primitive feedback polynomials provide the best performance. Some suggestions to avoid peaks in the aliasing probability are given.