系统级的可测性设计

随着IC设计的不断发展，SoC由于其可重用性而被广泛应用，这使得可测性设计（DFT）也被提高到系统级的高度。从顶层模块考虑，必须对不同模块采用不同的测试策略，合理分配测试资源。该文通过实例，提供了一种可行的系统级DFT方案。     

BIT技术的发展现状与应用分析

BIT技术的性能主要从故障探测、故障定位（针对单一的外场可更换单元）、虚假警报、以及错误诊断等方面加以说明。对于正确隔离故障来说,BIT所制定的目标会随着BIT等级的不同而有所变化。BIT等级越低,正确隔离故障的总体能力就越低;BIT等级越高,正确隔离故障的总体能力就越高。     

BIST-Based Delay-Fault Testing in FPGAs

We present the first delay-fault testing approach for Field Programmable Gate Arrays (FPGAs), applicable for on-line testing as well as for off-line manufacturing and system-level testing. Our approach is based on Built-In Self-Test (BIST), it is comprehensive, and does not require expensive external test equipment (ATE). We have successfully implemented this BIST approach for delay-fault testing on the Lattice ORCA 2C and Xilinx Spartan FPGAs.     

Design of ICs applying built-in current testing

Built-in Current (BIC) sensors have proven to be very useful in testing static CMOS ICs. In a number of experimental ICs BIC sensors were able to detect small abnormal I _DDQ currents. This paper discusses the design of the circuit under test and Built-in Current (BIC) sensors, which provide: maximum level of defect detectability, minimum impact of BIC sensor on the performance of the circuit under test and minimum area overhead needed for BIC sensors implementation.This research was supported by NSF Grant MIP8822805.     

Four different approaches for the measurement of IC surface temperature: application to thermal testing

Silicon die surface temperature can be used to monitor the health state of digital and analogue integrated circuits (IC). In the present paper, four different sensing techniques: scanning thermal microscope, laser reflectometer, laser interferometer and electronic built-in differential temperature sensors are used to measure the temperature at the surface of the same IC containing heat sources (hot spots) that behave as faulty digital gates. The goal of the paper is to describe the techniques as well as to present the performances of these sensing methods for the detection and localisation of hot spots in an IC.     

改进的大规模集成电路测试方法

为了提高大规模集成电路可测性设计（Design For Test,DFT）的故障覆盖率,减少测试时间,通过分析自我测试（Self-Testing Using MISR and Parallel SRSG,STUMPS）方法中的测试机制,找出了其测试效果不理想的原因,提出了改进型的大规模集成电路的测试方法,用C语言编写了故障模拟程序,并且在ISCAS’85标准测试电路上进行了验证。     

一种改进的嵌入式SRAM内建自测试设计

对单端口SRAM常用的13N测试算法进行修改和扩展,提出了一种适用于双端口SRAM的测试算法。该测试算法的复杂度为O(n),具有很好的实用性。作为一个实际应用,通过将该算法和13N测试算法实现于测试算法控制单元,完成了对片内多块单端口SRAM和双端口SRAM的自测试设计。     

济钢3500mm粗轧机嵌入式机架辊的研制与设计

济钢中厚板厂四辊轧机机架辊采用整体锻造箱体、嵌入式装配方式 ,结构紧凑。该结构有效的利用了有限的空间 ,不仅满足了轧制工艺的需要 ,而且保证了机架辊工作繁重、频繁启动、制动和承受轧件冲击的要求。与同类型的集中传动机架辊相比 ,嵌入式机架辊结构新颖、可靠。     

Facile construction of well-defined hierarchical NiFe2O4/NiFe layered double hydroxides with a built-in electric field for accelerating water splitting at the high current density

Interfacial charge redistribution induced by a strong built-in electric field can expertly optimize the adsorption energy of hydrogen and hydroxide for improving the catalytic activity. Herein, we develop a well-defined hierarchical NiFe₂O₄/NiFe layered double hydroxides (NFO/NiFe LDH) catalysts, exhibiting superior performance due to the strong interfacial electric field interaction between NiFe₂O₄ nanoparticle layers and NiFe LDH nanosheets. In 1 M KOH, NFO/NiFe LDH needs 251 mV and 130 to drive 50 and 10 mA cm^?2 for oxygen evolution reaction (OER) and hydrogen evolution reaction (HER). Moreover, only 1.517 V cell voltage is needed to reach 10 mA cm^?2 towards overall water splitting. Notably, under simulated industrial electrolysis conditions, NFO/NiFe LDH only needs 289 mV to drive 1000 mA cm^?2. This work puts a deep insight into the role of the built-in electric field in transition metal-based catalysts for accelerating water splitting and scalable industrial electrolysis applications.     

Mapping the built-in electric field in polymer light-emitting electrochemical cells

A millimeter planar polymer light-emitting electrochemical cell was turned on in a cryogenic probe station and subsequently cooled to freeze the doping profile. A 442 nm laser beam guided by an optical fiber was scanned across the interelectrode gap of several millimeters and the photovoltaic response was measured as a function of position. Both photocurrent and photovoltage profiles display a prominent peak at the geometric boundary of the p- and n-doped regions. A non-zero photovoltaic response throughout the p- and n-doped regions can be explained by various broadening mechanisms including non-uniform doping and secondary excitation by waveguided light. The photovoltaic response is weakest at the electrode/polymer interfaces.