Design of a PLL with improved locking range and its biomedical applications

This paper describes a phase locked loop employing a low voltage VCO using modified ECL inverter cells. The VCO circuit employed, features a positive feed back scheme to improve the operating frequency. The phase detector used in the PLL also uses a positive feedback scheme to improve the locked range and to reduce supply voltage of operation of the entire circuit. An improvement of locked range of around 35% was obtained from circuit simulation (using PSPICE) as well as from practical circuit, using discrete components. The minimum supply voltage required here is 2.5 volts. Some biomedical applications of this PLL are also proposed.     

Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-μm CMOS process

In these decades, integrated circuits for biomedical electronics applications have been designed and implemented in CMOS technologies. In order to be safely used by human, all microelectronic products must meet the reliability specifications. Therefore, electrostatic discharge (ESD) must be taken into consideration. To protect the biomedical integrated circuits in CMOS technologies from ESD damage, a dual-directional silicon-controlled rectifier (DDSCR) device was presented in this work. Experimental results show that the DDSCR has the advantages of high ESD robustness, low leakage, large swing tolerance, and good latchup immunity. The DDSCR was suitable for ESD protection in biomedical integrated circuits.     

High‐Performance Metal‐Substrate Power Module for Electrical Applications

This paper demonstrates the performance of a metal‐substrate power module with multiple fabricated chips for a high current electrical application, and evaluates the proposed module using a 1.5‐kW sinusoidal brushless direct current (BLDC) motor. Specifically, the power module has a hybrid structure employing a single‐layer heat‐sink extensible metal board (Al board). A fabricated motor driver IC and trench gate DMOSFET (TDMOSFET) are implemented on the Al board, and the proper heat‐sink size was designed under the operating conditions. The fabricated motor driver IC mainly operates as a speed controller under various load conditions, and as a multi‐phase gate driver using an N‐ch silicon MOSFET high‐side drive scheme. A fabricated power TDMOSFET is also included in the fabricated power module for three‐phase inverter operation. Using this proposed module, a BLDC motor is operated and evaluated under various pulse load tests, and our module is compared with a commercial MOSFET module in terms of the system efficiency and input current.     

Memristor emulator with tunable characteristic and its experimental results

In this study, operational transconductance amplifier (OTA) based simple and practical TiO₂ memristor emulator is presented. The proposed memristor emulator employs a multi-outputs OTA, an analog multiplier and a resistor and a capacitor. The parameters of the proposed memristor emulator can be tuned electronically by changing the biasing current of the OTA. Change of the transconductance gain of the OTA provides an advantage: “externally controllable memristor”. Non-volatile resistive switching characteristics and an application of this proposed memristor are given. Also, the memristor emulator is implemented using the commonly available OPA860. The effectiveness of the proposed memristor emulator is verified by the experimental results, which show good agreement with the theoretical and simulation results.     

A cascode modulated class-E power amplifier for wireless communications

A cascode modulated CMOS class-E power amplifier (PA) is presented in this paper. It is shown that by applying a modulated signal to the gate of the cascode transistor the output power is modulated. The main advantage of the proposed technique is a high 35 dB output power dynamic range. The peak power added efficiency (PAE) is 35%. The concept of the cascode power control of class-E RF PA operating at 2.2 GHz with 18 dBm output power was implemented in a CMOS technology and the performance has been verified by measurements. The prototype CMOS PA is tested by single tone excitation and by enhanced data rates for GSM evolution (EDGE) modulated signal. Digital predistortion is used to linearize the transfer characteristic. The EDGE spectrum mask is met and the rms error vector magnitude (EVM) is less than 4° in the entire output power range.     

1.5GHz CMOSECL输入接口的设计与测试

对一种高速CMOS ECL输入接口进行了分析研究,该接口包含一种双镜补偿的CMOS差分放大电路,采用0.18 μm CMOS工艺研制,实现了PECL电平兼容.经测试,该接口最高工作频率达1.5 GHz.     

一种双向、数字式微型无线内窥镜系统设计

通过分析目前消化道无线内窥镜的发展状况,提出了一种全新的双向、数字化的微型无线内窥镜系统方案设计,该系统具有实时观察病人图像、全消化道检查以及提供三维深度图像数据等功能,并对方案中各硬件模块及其关键技术进行了详细的论述,设计了该系统的FPGA验证环境,验证了整个方案的正确性。系统胶囊内的数模混合芯片已采用0.18μm CMOS工艺流片。     

一种带故障报警的漏电保护器电路设计

传统的小型漏电保护期没有故障自检功能,即使产品出现问题也没有告警。在这种情况下,如果真的有了漏电故障,就可能造成人身伤害,设备故障或者火灾。本设计利用常用的逻辑器件实现自动检测产品出现的故障功能,并给出故障报警。故障检测包括脱扣线圈检测,机械故障检测和内部的直流电源电路检测。     

New high accuracy CMOS current conveyors

In this paper, a new CMOS CCII⁺ is proposed. The circuit is characterized by high precision in voltage tracking and exhibits very low input resistance. An adaptive voltage offset cancellation methodology is introduced and then applied to the proposed circuit. As a result, a higher accuracy CCII⁺ is presented. For both circuits, the voltage offset cancellation is independent of the input current and voltage. To demonstrate the strength of the proposed architectures, fair comparisons with Liu and Yodprasit CCII realizations are held.     

A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

正A fully integrated multi-mode multi-band directed-conversion radio frequency(RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented.The front-end employs direct-conversion design,and consists of two differential tunable low noise amplifiers(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The two independent tunable LNAs are used to cover all the four frequency bands,achieving sufficient low noise and high gain performance with low power consumption.Switched capacitor arrays perform a resonant frequency point calibration for the LNAs.The two LNAs are combined at the driver stage of the mixer,which employs a folded double balanced Gilbert structure,and utilizes PMOS transistors as local oscillator(LO) switches to reduce flicker noise.The front-end has three gain modes to obtain a higher dynamic range.Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface(SPI) module.The frontend is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm~2.The measured doublesideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.