一种新型CMOS电流模带隙基准源的设计

设计了一种新型电流模带隙基准源电路和一个3bit的微调电路。该带隙基准源可以输出可调的基准电压和基准电流,避免了在应用中使用运算放大器进行基准电压放大和利用外接高精度电阻产生基准电流的缺点,同时该结构克服了传统电流模带隙基准源的系统失调、输出电压的下限限制以及电源抑制比低等问题。该带隙基准源采用0.5μm CMOS混合信号工艺进行实现,有效面积450μm×480μm;测试结果表明在3 V电源电压下消耗1.5mW功耗,电源抑制比在1 kHz下为72dB,当温度从-40～85°C变化时,基准电压的有效温度系数为30×10-6V/°C。该带隙基准电路成功应用在一款高速高分辨率模数转换器电路中。     

Integrated linear giga-ohm resistance using current scaling

Integrated grounded resistors of very large value are essential circuit elements for the design of compact filters with very low cut-off frequencies. A typical application of such filters is the rejection of DC voltages in amplifier circuits especially in physiological recording systems exhibiting electrode offset and low-frequency drift. In this letter, the implementation of a giga-ohm resistance is presented using a conventional fixed-gain OTA and a cascade of weak-inversion current scalers. The circuit yields a short design time, small power and area consumption as well as high linearity. A test circuit having an area of 0.011 mm² integrated in 0.35 μm CMOS is presented which yields a 41 Hz cut-off frequency, 1 V input range and less than −52 dB THD when connected to an integrated 1 pF capacitor, making it a suitable solution for the rejection of mains interference and offset in wearable biomedical applications.     

A low power 3.125 Gbps CMOS analog equalizer for serial links

A CMOS analog equalizer is designed to meet the different high speed communication specifications,such as USB 2.0,PCI-E and rapid IO.The proposed circuit architecture could facilitate the wide frequency scale ranging from 1 to 3.125 Gbps by adjusting the locations of pole and zero,so that the circuit can change its response accordingly as the channel characteristic alters.In order to balance the parasitic capacitors in the internal point,symmetric switches are addressed to generate the equal load for dif...     

CIS片上系统中伽玛校正的低功耗设计

为了实现CMOS图像传感器(CIS)片上系统(SoC)中伽玛(γ)校正的低功耗设计,同时又保证校正的精度,提出一种查找表和直线拟合相结合的γ校正技术。算法对灰度值较低的像素使用直接查找表方法校正,对于γ曲线上升缓慢部分的像素采用分段直线拟合的方法。在直线分段时,使用外层分段与内层分段相结合的方法,达到了分段优化的目的。算法保证了图像校正精度,与使用完全查找表法相比,误差在0.5 pixel之内。基于该方法设计了一个8 bit输入/8 bit输出的VLSI模块,通过FPGA对模块进行了验证,模块占用723个LE和195个LC寄存器,比完全查找表法减少了硬件资源耗费,实现了低功耗设计。系统最大工作频率可达148 MHz,完全满足实时处理的需求。     

CMOS compatible dual metal gate integration with successful Vth adjustment on high-k HfTaON by high-temperature metal intermixing

In this paper, we report for the first time a novel dual metal gate (MG) integration process for gate-first CMOS platform by utilizing the intermixing (InM) of laminated ultra-thin metal layers during high-temperature annealing at 1000 °C. In this process, an ultra-thin (2 nm) TaN film is first deposited on gate dielectric as a buffer layer. Preferable laminated metal stacks for NMOS and PMOS are then formed on a same wafer through a selective wet-etching process in which the gate dielectric is protected by the TaN buffer layer. Dual work function for CMOS can finally be achieved by the intermixing of the laminated metal films during the S/D activation annealing. To demonstrate this process, prototype metal stacks of TaN/Tb/TaN (NMOS) and TaN/Ti/HfN (PMOS) has been integrated on a single wafer, with WF of 4.15 and 4.72 eV achieved, respectively. Threshold voltage (V_th) adjustment and transistor characteristics on high-k HfTaON dielectric are also studied.     

A versatile signal flow graph realization of a general transfer function by using CDBA

A general synthesis procedure is given for a versatile signal flow graph realization of a general transfer function by using current differencing buffered amplifier (CDBA). The proposed configuration uses n+1 CDBAs, n capacitors and at most 2n+4 resistors. This number of resistors can be reduced to n+1 for special cases. The circuit is eligible to obtain a variety of transfer characteristics with the same common denominator polynomial, and it is easily converted to different modes of operations. It is straightforward to find the values of the passive elements from the coefficients of the transfer function to be realized. Simulations results are obtained by using commercially available active component AD844 and CMOS technology as well. All of these make the proposed circuit attractive.     

CMOS异或电路的设计与应用

设计了四种CMOS"异或"单元电路,通过模拟仿真分析了它们各自的性能特点,并讨论了它们在奇偶检测电路、微处理器系统加法器电路以及单片机全加电路等设计中的不同应用.     

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a g_m/I_D based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.     

Multiphase sinusoidal oscillators using second generation current conveyors

A voltage-mode Multiphase Sinusoidal Oscillator realized using Second Generation Current Conveyors and only grounded passive elements is introduced in this paper. The proposed topology is suitable for realizing oscillators with both odd and even number of phases without modifying the core of the topology. Only non-inverting Current Conveyors are required for the construction of the oscillator's topology and this is a benefit from the discrete component implementation point of view. The behavior of the proposed topology has been evaluated, through experimental results, in the cases of three and six-phase oscillators.