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31.
Bafleur M. Vidal M. Puig Buxo J. Givelin Ph. Macary V. Sarrabayrouse G. 《Analog Integrated Circuits and Signal Processing》1995,8(3):219-231
To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown. 相似文献
32.
Giuseppe Ferri 《Analog Integrated Circuits and Signal Processing》2002,33(3):249-262
In this paper the author will present the working principle and the applications of a novel adaptive biasing topology, designed to decrease the stand-by power dissipation without affecting the transient performance of low-power amplifiers. The proposed circuit, whose principle and circuit topology can be implemented both in CMOS and in bipolar standard technologies, gives a biasing current whose value depends on the applied input differential voltage and can be set according to the requested transient performance constraints. The adaptive architecture can be utilized in the design of high-efficient low-power operational amplifiers, for the biasing of both the input stage (where the input source current is dynamically increased) and the output stage (where the output current can be controlled and limited). These amplifiers show a very good behaviour, evaluated in terms of two efficiency factors, if compared with those of other adaptive solutions and class-AB topologies, proposed in the literature. Simulation results and also measurements on a chip prototype, fabricated in a standard CMOS technology, are finally presented. 相似文献
33.
Summary A derivation of a parallel algorithm for rank order filtering is presented. Both derivation and result differ from earlier designs: the derivations are less complicated and the result allows a number of different implementations. The same derivation is used to design a collection of priority queues. Both filters and priority queues are highly efficient: they have constant response time and small latency.
Anne Kaldewaij received an M.Sc. degree in Mathematics from the University of Utrecht (The Netherlands) and a Ph.D. degree in Computing Science from the Eindhoven University of Technology. Currently, he is associate professor in Computing Science at Eindhoven University. His research includes parallel programming and the design of algorithms and data structures. He enjoys teaching and he has written a number of textbooks on mathematics and programming.
Jan Tijmen Udding received an M.Sc. degree in Mathematics in 1980 and a Ph.D. degree in Computing Science in 1984 from Eindhoven University of Technology. Currently, he is associate professor at Groningen University. His main research interests are mathematical aspects of VLSI, program derivation and correctness, and functional programming. 相似文献
34.
Asynchronous design techniques have a number of compelling features that make them suited for complex system on chip designs. However, it is necessary to develop practical and efficient design techniques to overcome the present shortage of commercial design tools. This paper describes the development of CADRE (Configurable Asynchronous DSP for Reduced Energy), a 750K transistor, high performance, low-power digital signal processor IP block intended for digital mobile phone chipsets. A short time period was available for the project, and so a methodology was developed that allowed high-level simulation of the design at the earliest possible stage within the conventional schematic entry environment and simulation tools used for later circuit-level performance and power consumption assessment. Initial modeling was based on C behavioral models of the various data and control components, with the many asynchronous control circuits required automatically generated from their specifications. This has enabled design options to be explored and unusual features of the design, such as the Register Bank which is designed to exploit data access patterns, are presented along with the power and performance results of the processor as a whole. 相似文献
35.
通过混合集成型结构光学拾音器的光学设计和芯片设计,制作了包含微光学棱镜,光电探测器和信号放大电路的混合集成型光学拾音器。经过测试,发现有较好的信号输出特性,表明混合集成型光学拾音器已基本研制成功。 相似文献
36.
本文首次提出一种新观点,超大规模集成电路中互连结构的等效模型应具有层次性,对于底层的电路设计,应将互加看作一种具有分布参数的多端口网络,而对于高层次的模块设计,则应将互连看作一种逻辑元件,基于这种观点,本文提出了一种表格型的逻辑模型,它可以将互连产生的三种主要负效应:串扰、延迟和信号变形人武部考虑在内。 相似文献
37.
采用了TSMC0.35μm CMOS工艺实现了可用于SONET/SDH2.5Gb/s和3.125Gb/s速率级光纤通信系统的限幅放大器。通过在芯片测试其最小输入动态范围可达8mVp—p,单端输出摆幅为400mVp-p,功耗250mW,含信号丢失检测功能,可以满足商用化光纤通信系统的使用标准。 相似文献
38.
Rui Morimoto Chisato Yokomori Akiko Kikkawa Akira Izumi Hideki Matsumura 《Thin solid films》2003,430(1-2):230-235
In this paper, bulk-Si metal–oxide–semiconductor field effect transistors (MOSFETs) are fabricated using the catalytic chemical vapor deposition (Cat-CVD) method as an alternative technology to the conventional high-temperature thermal chemical vapor deposition. Particularly, formation of low-resistivity phosphorus (P)-doped poly-Si films is attempted by using Cat-CVD-deposited amorphous silicon (a-Si) films and successive rapid thermal annealing (RTA) of them. Even after RTA processes, neither peeling nor bubbling are observed, since hydrogen contents in Cat-CVD a-Si films can be as low as 1.1%. Both the crystallization and low resistivity of 0.004 Ω·cm are realized by RTA at 1000 °C for only 5 s. It is also revealed that Cat-CVD SiNx films prepared at 250 °C show excellent oxidation resistance, when the thickness of films is larger than approximately 10 nm for wet O2 oxidation at 1100 °C. It is found that the thickness required to stop oxygen penetration is equivalent to that for thermal CVD SiNx prepared at 750 °C. Finally, complementary MOSFETs (CMOSs) of single-crystalline Si were fabricated by using Cat-CVD poly-Si for gate electrodes and SiNx films for masks of local oxidation of silicon (LOCOS). At 3.3 V operation, less than 1.0 pA μm−1 of OFF leakage current and ON/OFF ratio of 107–108 are realized, i.e. the devices can operate similarly to conventional thermal CVD process. 相似文献
39.
40.
Moritoshi Yasunaga Noriyuki Aibe Yoshiki Yamaguchi Yorihisa Yamamoto Takaaki Awano Ikuo Yoshihara 《Artificial Life and Robotics》2008,12(1-2):219-222
Watching and tracking an object while seeing a much wider view is one of advantages of the eye system. We proposed and developed
a tracking camera system that mimics the eyes by using double-lens modules. In the system, a wide view is captured through
the wide-lens module, while the target in it is tracked and magnified through the telescopic lens module. Electronic circuits
for tracking control are implemented onto the reconfigurable VLSI or FPGA in order to embed the parallelism in the tracking
algorithm into the hardware. A successfully developed FPGA-based prototype performs high-speed tracking at the video-rate.
This work was present in part at the 12th International Symposium on Artificial Life and Robotics, Oita, Japan, January 25–27,
2007 相似文献