Modular implementation of efficient self-checking checkers for the Berger code

A technique for designing efficient checkers for conventional Berger code is proposed in this paper. The check bits are derived by partitioning the information bits into two blocks, and then using an addition array to sum the number of 1's in each block. The check bit generator circuit uses a specially designed 4-input 1's counter. Two other types of 1's counters having 2 and 3 inputs are also used to realize checkers for variable length information bits. Several variations of 2-bit adder circuits are used to add the number of 1's. The check bit generator circuit uses gates with fan-in of less than or equal to 4 to simplify implementation in CMOS. The technique achieves significant improvement in gate count as well as speed over existing approaches.     

一种带接口的CMOS10位电流型乘法D／A转换器

介绍了一种带接口的单片ＣＭＯＳ１０位电流型乘法Ｄ／Ａ转换器的设计及工作方式。着重阐述逻辑电平转换、控制逻辑的结构设计及其工作方式。在不修调电阻网络的情况下，该Ｄ／Ａ转换器在５Ｖ、１５Ｖ下，其线性误差、微分误差、满刻度误差均能达到１０位精度     

MPEG-4视频解码器中IDCT模块的MMA前端设计

面向移动多媒体终端SOC设计了一种二维IDCT硬件加速器,基于快速LLM算法实现了8点IDCT运算,使用单RAM转置存储器进行行列分解,采用流水线技术,提高了处理速度,同时降低了芯片面积。     

低功耗并行LTE-Turbo译码器的VLSI结构设计及实现

针对3GPP LTE标准中的Turbo码,设计了一种基于最大后验概率算法的低功耗并行译码器.根据二次置换多项式交织器的整数数学特性,分解并行处理中每个译码器的交织地址为子码块地址和块内偏移地址,提出一种高效的递归计算子码块交织地址的算法,使得并行度可以为任意值,而不仅仅限于2的幂次;并依此设计了低复杂度的实时递归计算交织器的互连结构,以避免传统实现方法中对交织地址的存储,有效地简化了Turbo译码器本征信息处理的互连网络,减小了实现面积和功耗;最后从结构级进行优化设计,进一步减少面积和功耗.实验结果表明,在40nm的工艺下,约束工作电压为1.18V、时钟频率为282MHz,版图实现可以达到130Mb/s的吞吐量,且功耗仅为107mW,每次迭代能量效率为0.107nJ/bit.     

A preliminary study of a diagonal channel-routing model

The layout of two-terminal nets in a VLSI channel is realized in a new diagonal channel-routing model (DCRM), where the tracks are segments respectively displayed at +45 ° and –45 ° on the two layers of the channel. A new definition of channel density is introduced, and a lower bound to the channel width is derived by the application of an algorithm, whose complexity is evaluated as a function of the channel density, and other parameters of the problem.A simple linear-time algorithm is proposed, which produces an optimal layout (i.e., it requires a channel of minimum width) if the length of the longest net equals the lower bound for the channel width. In any case, the number of vias is at most one for each net. Some particular solutions are proposed for problems with long nets.Specific problems are much easier in DCRM than in the classical Manhattan model. For example, any shift-by-i can be realized in DCRM in a channel of widthi.This work has been supported by Consiglio Nazionale delle Ricerche of Italy under a research grant.     

基于CMOS工艺的无线图像传感器网络综述

无线传感器网络是无线通讯技术、网络技术、传感器技术交叉融合的新兴产物。无线传感器网络具备小型化、智能化、网络化和能够无线通讯等特点,能够满足人们在生产生活、科学研究、军事、医疗等众多领域对于实时信息获取的需求。由于人类获取信息的80%以上是通过视觉获取的,因此,无线图像传感器网络作为人类获取视觉图像信息的重要工具在无线传感器网络中占有重要的地位。无线图像传感器网络要想实现小型化、智能化、集成化等要求,采用与标准CMOS工艺兼容的CMOS图像传感器技术将是最为理想的选择。随着CMOS图像传感器工艺和设计水平的进步,CMOS图像传感器在成像质量、生产成本、小型化、智能化等方面显示出巨大的优势,同时由于与VLSI电路兼容的天然特性,基于CMOS图像传感器的无线图像传感器网络拥有巨大的发展潜力和广阔的市场前景。基于CMOS的无线图像传感器网络目前呈现多元化的发展趋势,高分辨率、高速、低功耗、智能化等方向是基于CMOS的无线图像传感器网络未来发展的方向。     

基于CMOS模拟开关实现平衡混频器

详细介绍了有源单平衡混频器的电路组成,分析了有源平衡混频器的工作原理。基于CMOS模拟开关设计实现了一种(低功耗、高线性度的)开关平衡混频器,最后对混频器的指标进行了测量和分析。测试结果表明(在3.3V电源电压下,消耗电流小于10mA,射频输入信号)在60～110MHz频带范围内,(本振信号+10dBm时)插入损耗小于7dB,波动小于1dB,输入P1dB压缩点大于13dBm。     

On problem transformability in VLSI

The two basic performance parameters that capture the complexity of any VLSI chip are the area of the chip,A, and the computation time,T. A systematic approach for establishing lower bounds onA is presented. This approach relatesA to the bisection flow, . A theory of problem transformation based on , which captures bothAT ² andA complexity, is developed. A fundamental problem, namely, element uniqueness, is chosen as a computational prototype. It is shown under general input/output protocol assumptions that any chip that decides ifn elements (each with (1+)lognbits) are unique must have =(nlogn), and thus, AT²=(n ²log² n), andA= (nlogn). A theory of VLSI transformability reveals the inherentAT ² andA complexity of a large class of related problems.This work was supported in part by the Semiconductor Research Corporation under contract RSCH 84-06-049-6.     

医用内窥镜微型摄像模组设计

设计了一种新型医用内窥镜微型摄像模组.该模组采用微型、高分辨率的CMOS图像传感器结合低压差分信号（LVDS）传输技术进行设计,使摄像模组直径缩减至5.0mm,并实现了图像数据的长距离高保真传输.搭建了实验平台对摄像模组的摄像功能进行了测试.结果表明：该模组图像传输距离超过2m,分辨率达到30万像素,对口腔溃疡模拟粘膜病变的识别率高达90％.其图像分辨率高,传输距离长,使其适用于内镜诊断;其直径小,能大大提高病人内镜检查的舒适性,为超细内镜诊断提供了一种极佳的解决方案.