CMOS图像传感器中的串扰与常用解决方案

CMOS图像传感器中,串扰的大小会影响到图像传感器最终输出图像的质量,串扰越大,最终的图像质量越差,并随着目前像素单元尺寸的逐渐减小,光串扰和电荷串扰都会越来越严重。针对CMOS图像传感器中存在的这2种形式的串扰,结合具体的应用环境,出现了各种各样的解决方案。这些方案多从器件结构改进和材料等方面着手,采取有效措施,将CMOS图像传感器在具体场合应用时的串扰降低到了一个合理的水平。     

基于超图模型的大规模门级网表层次化聚类算法

为了克服现有层次化方法通用性差、运算效率不高、电路结构提取不准等缺点,提出了一种基于超图模型的层次化聚类算法.首先对网表中最基本的迭代、总线、扇入和串联结构进行自动识别,然后将这4种基本结构按不同的组合方式进行多级聚类,最终建立起了网表的层次化结构.由于文中基本结构聚类算法是专门针对超图数据结构设计的,其时间复杂度较低.实验结果表明,该算法既可以得到较准确的层次信息,又能保证较高的运算速度,对各种应用均有较好的效果.     

聚酰亚胺电容式湿度传感器的制备工艺研究

改变传统丝网印刷制作电极的方法,采用正胶反刻、干湿结合的CMOS工艺研制出了以聚酰亚胺为感湿介质的相对电容式湿度传感器。并对其结构进行了理论分析,确定了湿度传感器的工艺步骤和版图设计。对其测量范围、湿滞和响应时间进行了测试。通过实验结果与模拟结果的对比分析,给出了该实验中存在的问题和改进意见。     

VLSI and SPICE modeling of ALU

The Arithmetic and Logic Unit （ALU） is a combination circuit that performs a number of arithmetic and logical operations within a microprocessor. The demand for faster and compact ALUs makes it desirable to test the ALU in conjunction with pre-design parts prior to manufacture. This may be accomplished in a process using CAD and SPICE simulation software. Our purpose is to realize a method for importing a layout drawn in Tanner L-edit and simulated in T-Spice into PSpice which is referred to as software talking. To do so we use an eight-function instruction set called Complimentary Metal Oxide Semiconductor Arithmetic and Logic Unit （CMOS ALU） which is laid out in Tanner L-edit and produces an extracted net-list which is simulated in T-Spice. An ALU equivalent design is then modeled in PSpice for further testing with pre-manufactured parts of the PSpice library.     

数值协处理器微码电路的分析与检测

主要讨论用于完成数值协处理器各种运算的微码电路。简单介绍微码电路在协处理器中的重要性,具体介绍微程序控制模块的工作原理,微码电路的微码地址产生、微程序和微子程序的调用、四阈值微码的译码及微码电路的检测电路。     

矩阵求逆运算的VLSI实现

矩阵运算广泛应用于各类电路计算中,矩阵运算的硬件实现能够充分发挥硬件的速度和并行性。其中矩阵求逆是矩阵运算中重要的运算。为加速矩阵求逆,研究构造出一种非常易于实现的基于心动阵列的矩阵求逆的电路结构。通过硬件描述语言Verilog建模,VCS仿真及用Design Compile进行综合,结果表明这种并行结构能快速实现矩阵求逆,且运算精度较高。     

生物／化学微传感器技术和应用（二）

本文综述了生物／化学微传感器的技术和应用,详细描述了起源于半导体技术的标准工艺流程和制造三维机械结构的特殊微细机加工工艺,给出了基本化学传感器原理和对应的化学／生物传感器应用实例,最后提出了单片集成化学／生物微传感器系统,包括单一芯片上传感器结构和运转电路。     

基于时间域读出的大动态范围CMOS图像传感器

设计了一款基于时间域读出的大动态范围CMOS图像传感器。传感器基于一种新型的结构,其可在时间域下探测高输入光强,在模拟域下探测低输入光强。该设计在传统电容反馈式跨阻放大器(CTIA)的基础上,新增了时间域测量电路,在不改变原有积分过程的同时可实现连续的大动态范围。基于0.35μm,5V-CMOS工艺进行了256×1线列CMOS图像传感器流片,光电二极管面积为22.5μm×22.5μm,并对器件的光电特性进行了后仿真验证。仿真测试结果表明,基于时间域读出的图像传感器可实现96dB的大动态范围,且时间域和模拟域的两路输出信号可同步输出,功耗为7.98mW。     

基于标准CMOS工艺的片上太阳敏感器研究

微纳卫星对于载荷的苛刻要求使得太阳敏感器的微型化研究具有重要意义。为了解决光学器件和处理电路的集成兼容问题,文章基于标准CMOS工艺提出一种新型片上太阳敏感器,以金属走线层构建微型墙结构,两侧均匀分布pn结构成光电传感器,通过检测两侧光电流比例解算出入射光角度。文章从工艺实现、模型建立、数值仿真和实验测试等方面验证了器件的合理性和可行性。最终,片上太阳敏感器阵列芯片质量为1.5g,尺寸为304.2mm³,检测精度为±1.6°,视场范围为80°,可满足微型化需求。     

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

Continuous improvements in very-large-scale integration (VLSI) technology and design software have significantly broadened the scope of digital signal processing (DSP) applications. The use of application-specific integrated circuits (ASICs) and programmable digital signal processors for many DSP applications have changed, even though new system implementations based on reconfigurable computing are becoming more complex. Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation (DWT) and sophisticated computerized design techniques, which are much needed in today’s modern world. New research and commercial efforts to sustain power optimization, cost savings, and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged. Hence, in this paper, it is proposed that the DWT method can be implemented on a field-programmable gate array in a digital architecture (FPGA-DA). We examined the effects of quantization on DWT performance in classification problems to demonstrate its reliability concerning fixed-point math implementations. The Advanced Encryption Standard (AES) algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks (ANN) method. By reducing hardware area by 57%, the proposed system has a higher throughput rate of 88.72%, reliability analysis of 95.5% compared to the other standard methods.