Hardware assisted watermarking for multimedia

Digital media offer several distinct advantages over analog media, such as high quality, ease of editing, and ease of processing operations such as compression and high fidelity copying. Digital data is commonly available through digital TV broadcast, CD, DVD, and computing devices such as personal computers. The ease by which a digital media object can be duplicated and distributed has led to the need for effective digital rights management tools. Digital watermarking is one such tool. Watermarking is the process of embedding extra data called a watermark into a multimedia object, like image, audio, or video, such that the watermark can later be detected or extracted in order to make an assertion regarding the object. During the last decade, numerous software based watermarking schemes have appeared in the literature and watermarking research has attained a certain degree of maturity. But hardware based watermarking systems have evolved more recently only and they are still at their infancy. The goal of hardware assisted watermarking is to achieve low power usage, real-time performance, reliability, and ease of integration with existing consumer electronic devices. In this paper, we survey the hardware assisted solutions proposed in the literature for watermarking of multimedia objects. The survey is preceded by an introduction to the background issues involved in digital watermarking.     

应用于RFID的超低功耗CMOS温度传感器设计

针对融合射频识别( RFlD)的无线温度传感器节点设计的需求,采用0. 18μm 1P6M台积电CMOS工艺,设计了一种低功耗集成温度传感器.该温度传感器首先将温度信号转换为电压信号,然后通过经压控振荡器将电压信号转换为受温度控制的频率信号,再通过计数器,将频率信号转换为数字信号.传感器电路利用MOS管工作在亚阈值区,并采用动态阈值技术获得超低功耗.测试结果显示:所设计的温度传感器仅占用0. 051 mm2 ,功耗仅为101 nW,在0~100℃范围内误差为-1. 5~1. 2℃.     

金标试纸条的尿素酶快速定量检测仪研制

研制了一种基于CMOS传感器的胶体金免疫层析试纸条的尿素酶定量检测系统。该系统由硬件和软件两部分组成,硬件部分利用CMOS传感器和条码扫描仪来获取检测图像和病人的个人信息。软件部分除了实现免疫层析试纸条光信号的分析和诊断还实现病人信息采集和建立病人信息数据库等关键功能。该软件采用了k-means聚类算法,实现采集图像的精准分析。通过检测200例尿素酶样品试纸条,验证了设备的稳定性和准确性。该系统体积小、便携性强且具有优秀的续航能力,可用于长时间的临床、野外和社区体检。     

基于标准CMOS工艺太阳能电池的微电源管理系统

文章基于CMOS太阳能电池设计了一款微电源管理系统。此电源管理系统适用于传感器网络节点和半有源电子标签之类的需要周期性短时间供电的电路。电源管理系统中包含一个电荷泵,一个片外储能电容,控制电路和一个线性稳压器。控制电路采用一种全新的结构,静态功耗基本为零。采用UMC 0.18μm CMOS工艺,当输出电流为30uA,储能电容为1uF时,一个周期可达到大于20ms的供电时间,输出电压1.8V,电源管理系统的静态电流小于1.5uA。     

The Asynchronous Bounded-Cycle model

This paper shows how synchrony conditions can be added to the purely asynchronous model in a way that avoids any reference to message delays and computing step times, as well as system-wide constraints on execution patterns and network topology. Our Asynchronous Bounded-Cycle (ABC) model just bounds the ratio of the number of forward- and backward-oriented messages in certain (“relevant”) cycles in the space-time diagram of an asynchronous execution. We show that clock synchronization and lock-step rounds can be implemented and proved correct in the ABC model, even in the presence of Byzantine failures. Furthermore, we prove that any algorithm working correctly in the partially synchronous Θ-Model also works correctly in the ABC model. In our proof, we first apply a novel method for assigning certain message delays to asynchronous executions, which is based on a variant of Farkas’ theorem of linear inequalities and a non-standard cycle space of graphs. Using methods from point-set topology, we then prove that the existence of this delay assignment implies model indistinguishability for time-free safety and liveness properties. We also introduce several weaker variants of the ABC model, and relate our model to the existing partially synchronous system models, in particular, the classic models of Dwork, Lynch and Stockmayer and the query-response model by Mostefaoui, Mourgaya, and Raynal. Finally, we discuss some aspects of the ABC model’s applicability in real systems, in particular, in the context of VLSI Systems-on-Chip.     

对DAG-MAP算法的研究

DAG－MAP是一个面向延迟优化的FPGA工艺映射算法,其中的标记过程是该算法的核心.文章对原算法中的标记过程进行了研究,并且提出了一个改进的标记方法.通过对MCNC标准测试电路的实验结果表明该算法比原算法更为有效,并且算法所用时间没有明显的增加.     

基于DVS机制的低能耗微处理器系统设计方法研究

能耗已经成为微处理器设计的最大挑战之一。微处理器的能耗在便携设备中占有重要的比例。DVS（Dynamic Voltage Scaling）机制可以在设备运行过程中,通过降低处理器的工作电压来降低它的能耗。同时,还需降低处理器的速度。电压调度程序通过分析应用的约束和需求来给定适当的工作电压。文章论述了速度和输入电压可变的微处理器系统设计方法。在处理器低速工作时,降低工作电压可以大幅度降低它的能耗。这将使应用系统能快速地根据负荷的变化调节处理器的性能。     

一种新的CMOS组合电路最大功耗快速模拟方法

过大的峰值功耗会使芯片承受过大的瞬间电流冲击,降低芯片的可靠性及性能,因此有效地对电路最大功耗做出精确的估计非常重要。由于在实际电路中存在的时间延迟,而考虑延时的电路功耗模型计算量较大,因此用模拟方法求取电路最大功耗非常耗时。为了在尽可能短的时间内对VLSI电路的最大功耗做出较为可信的估计,首次提出了二阶段模拟加速方法。对ISCAS85电路集的实验结果表明,这种估计方法具有最大功耗估计值准确和加速明显的优点。     

Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation

In this paper, we propose evolvable reasoning hardware and its design methodology. In the proposed design methodology, case databases of each reasoning task are transformed into truth tables, which are evolved to extract rules behind the past cases through a genetic algorithm. Circuits for the evolvable reasoning hardware are synthesized from the evolved truth-tables. Parallelism in each task can be embedded directly in the circuits through the direct hardware implementation of the case databases. We developed the evolvable reasoning hardware prototype using Xilinx Virtex FPGA chips and applied it to the English-pronunciation-reasoning (EPR) task. The evolvable reasoning hardware for the EPR task was implemented with 270K gates, achieving an extremely high reasoning speed of less than 300 ns/phoneme. It also achieved a reasoning accuracy of 82.1% which is almost the same accuracy as NETTalk in neural networks and MBRTalk in parallel AI.     

Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits

A concept for a future integer arithmetic unit suitable for a realization with 3-D optoelectronic very large scale integrated (VLSI) circuits is presented. Due to the use of optical interconnections running vertically to the circuit's surface no pin limitation is given. This allows massively parallelism and a higher throughput performance than in all-electronic solutions. To exploit the potential of optical interconnections in VLSI systems efficiently well-adapted low-level algorithms and architectures have to be developed. This is demonstrated for a pipelined arithmetic unit using a redundant number representation. A transistor layout for the optoelectronic circuits is given as well as a specification for the necessary optical interconnection scheme linking the circuits with free-space optics. It is shown that the throughput can be increased by a factor of 10 to 50 compared to current all-electronic processors by considering state-of-the-art optical and optoelectronic technology. Furthermore we present results we gained by investigations on a first realized optoelectronic VLSI test chip.