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991.
《Microelectronics Journal》2015,46(11):1039-1045
A new CMOS differential current-mode AGC on the division operation based is presented. The operation principle consists in detection of both positive and negative envelopes of the differential input signal cycles, respectively. The output signal with constant magnitude is obtained by dividing the differential input signal to the difference between the positive and negative detected envelopes. The new current-mode architecture of the proposed AGC (composed only by an envelope detector and a divider stage) diminishes significantly the settling time, the circuit complexity and the power consumption. The circuit yields an input dynamic range of 15 dB and provides a constant magnitude output signal in the frequency range from 10 MHz to 70 MHz. The current consumption is 5 mA from a single 3.3 V supply voltage. The simulations performed in 0.13 µm CMOS process confirm the theoretically obtained results. 相似文献
992.
《Microelectronics Journal》2015,46(2):198-206
In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second- and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain, -3 dB bandwidth (BW−3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of +13.1 dBm and +42.8 dBm, respectively. The simulated S11 is less than −11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply. 相似文献
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996.
A circuit system of on chip BP(Back-Propagation) learning neural network with pro grammable neurons has been designed,which comprises a feedforward network,an error backpropagation network and a weight updating circuit. It has the merits of simplicity,programmability, speedness,low power-consumption and high density. A novel neuron circuit with pro grammable parameters has been proposed. It generates not only the sigmoidal function but also its derivative. HSPICE simulations are done to a neuron circuit with level 47 transistor models as a standard 1.2tμm CMOS process. The results show that both functions are matched with their respec ive ideal functions very well. The non-linear partition problem is used to verify the operation of the network. The simulation result shows the superior performance of this BP neural network with on-chip learning. 相似文献
997.
A new pulse stream neuron circuit is presented, which can be obtained in the digital CMOS process and combines both the merits of digital circuits and analog ones. The output is expressed by the frequency of the pulses with transfer characteristic, which is correspondent with the ideal sigmoid curve perfectly. Moreover, the pulse-active strategy is introduced into the design of this CMOS pulse stream neuron circuit for the first time in order to reduce the power dissipation, which is applicable to the low-power design of mixed-signal circuits,too. A simple technical process and compact architecture make this circuit work at a higher speed and with lower power dissipation and smaller area. 相似文献
998.
提出实现VLSI的PSSWS(Poly Silicon Side Wall Spacer)—LDD(Lightly DopedDrain)结构,研究了它的形成工艺,获得多晶侧壁形成的优化工艺条件,制作出亚微米有效沟道长度的LDD NMOSFET。在器件性能研究和计算机模拟的基础上,得到PSSWS—LDDMOSFET的优化工艺实现条件;此条件下实现的有效沟道长为0.8μm的PSSWS—LDDNMOSFET,源漏击穿电压达20V,常规器件的小于16V;衬底电流较常规器件的减小约二个数量级。利用此优化条件,研制出高性能的1μm沟道长度的CMOS CD4007电路,2μm沟道长的21级CMOS环振,LSI CMOS 2.5μm沟道长度的门阵列电路GA 300 5SD。结果表明:PSSWS—LDD MOSFET性能衰退小,速度快,可靠性高,适用于VLSI的制造。 相似文献
999.
Design and fabrication of Schottky barrier diodes (SBD) with a commercial standard 0.35μm CMOS process are described.In order to reduce the series resistor of Schottky contact,interdigitating the fingers of schottky diode layout is adopted.The I-V,C-V,and S parameter are measured.The parameters of realized SBD such as the saturation current,breakdown voltage,and the Schottky barrier height are given.The SPICE simulation model of the realized SBDs is given. 相似文献
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