CMOS全差分超宽带低噪声放大器

文中给出了一个应用于超宽带射频接收机中的全集成低噪声放大器,该低噪声放大器采用了电阻并联负反馈与源极退化电感技术的结合,为全差分结构,在Jazz0.18μm RF CMOS工艺下实现,芯片面积为1.08mm2,射频端ESD抗击穿电压为1.4kV。测试结果表明,在1.8V电源电压下,该LNA的工作频带为3.1～4.7GHz,功耗为14.9mW,噪声系数(NF)为1.91～3.24dB,输入三阶交调量(IIP3)为-8dBm。     

CMOS图像传感器接口

文中介绍基于ARM core的SOC芯片中CMOS图像传感器接口IP模块的设计方案.该IP模块连接在AHB总线和外部的CMOS图像传感器之间,完成对高速图像数据的采集和传输,并能够为后续的图像处理提供统计数据.经过验证,该模块可以完成每帧200万像素的图像数据传输.     

基于倍增技术的超低压高精度CMOS开关设计

设计一种能够工作在超低电源电压下的CMOS开关.该结构运用电压倍增器获得高压,此高压使开关产生的恒定大跨导和大信号摆幅能够在低压电路中传输信号,虚拟开关提高了信号传输精度.在分析电路工作机理的基础上,结合0.35μm标准工艺模型优化了电路参数.合理的电路结构设计和版图设计增加了电路的使用寿命.理论分析和Hsp ice模拟结果表明:该结构能够在低于1 V电源电压下工作,虚拟开关的应用使信号传输精度从69%提高到99.7%.该结构实现了低压下高精度的模拟开关设计.     

一种Si CMOS的Ka波段毫米波功率放大器

为了满足毫米波雷达或通信系统对更高发射功率的需求,基于65 nm Bulk Si CMOS工艺制程设计了一款Ka频段功率放大器.该功率放大器工作于30～32 GHz,采用了共源共栅差分对结构的两级放大单元,使用中和电容增强电路的稳定性,并以变压器为基础设计实现了片上无源阻抗匹配网络.经过测试,该功率放大器在工作频段内的...     

Dielectrophoresis‐Assisted Integration of 1024 Carbon Nanotube Sensors into a CMOS Microsystem

Carbon‐nanotube (CNT)‐based sensors offer the potential to detect single‐molecule events and picomolar analyte concentrations. An important step toward applications of such nanosensors is their integration in large arrays. The availability of large arrays would enable multiplexed and parallel sensing, and the simultaneously obtained sensor signals would facilitate statistical analysis. A reliable method to fabricate an array of 1024 CNT‐based sensors on a fully processed complementary‐metal‐oxide‐semiconductor microsystem is presented. A high‐yield process for the deposition of CNTs from a suspension by means of liquid‐coupled floating‐electrode dielectrophoresis (DEP), which yielded 80% of the sensor devices featuring between one and five CNTs, is developed. The mechanism of floating‐electrode DEP on full arrays and individual devices to understand its self‐limiting behavior is studied. The resistance distributions across the array of CNT devices with respect to different DEP parameters are characterized. The CNT devices are then operated as liquid‐gated CNT field‐effect‐transistors (LG‐CNTFET) in liquid environment. Current dependency to the gate voltage of up to two orders of magnitude is recorded. Finally, the sensors are validated by studying the pH dependency of the LG‐CNTFET conductance and it is demonstrated that 73% of the CNT sensors of a given microsystem show a resistance decrease upon increasing the pH value.     

采用超低失调运放的集成积分器的设计与实现

采用特殊技术方法控制二级运放中特定MOS管尺寸,设计出一种超低失调电压的运算放大器,并将其应用到集成积分器的设计.然后基于理想积分器的工作原理,用一种新的方法,设计并实现了一种有超低失调运放的集成积分器.设计采用HHNEC0.18μm CMOS工艺,在Cadence环境下利用Hspice进行仿真,结果显示,运放失调为556nV,增益以及相位稳定裕度较大;积分器在1kHz频率工作时显示出良好的工作特性.版图设计考虑了失配与匹配的问题,并且通过了DRC和LVS规则检查.     

Lower-error and area-efficient antilogarithmic converters with bit-correction schemes

In this article, we have proposed fast lower-error and area-efficient antilogarithmic converters. By employing new approximation schemes with two-region shift-and-add operations, our proposed converters can perform high-speed conversions from logarithmic numbers to binary numbers. Synthesis results show that our proposed converters can achieve time savings of over 32.5% and can save 42.3% of the area used compared with previously proposed methods. In addition, the percent error ranges for various logarithmic number system (LNS)-based operations used by our proposed logarithmic processor are lower than those of previous methods. Our proposed converters can be applied to LNS-based processors to ease the tremendous computation overhead and boost the performance.     

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability.In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology.Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties.It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling.In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices.Therefore, detailed atomicscale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks,are highly required.In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed.Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy (HRTEM) and the related techniques based on scanning transmission electron microscopy (STEM), including high-angle annular darkfield (HAADF) imaging (also known as Z-contrast imaging), electron energy-loss spectroscopy (EELS), and energy dispersive X-ray spectroscopy (EDS), due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices.In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics.In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed.The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4.Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.     

一种嵌入式系统软件水印识别器的VLSI实现

提出了一种基于分支软件水印方案识别器的VLSI实现.硬件形式的识别器一般难以获取嵌入式系统内部的函数返回地址,通过改进获取指纹信息分支函数(FBF)入口的方法,使得只需要根据系统的程序指针和指令字就可以完成FBF函数入口的识别,使原有方法更适用于嵌入式系统.最后针对所支持的指令集进行了仿真测试,并对设计实现进行了逻辑综合.性能分析表明,硬件形式识别器识别速度远远超过软件的识别速度.     

高速数字化三维集成式CCD-CMOS图像传感器

为了解决CCD与CMOS工艺兼容性低、互连集成制作难度大,以及芯片间接口匹配和高性能兼备等问题,对CCD器件拓扑结构与像元、CMOS读出电路、三维异质互连集成及高密度引脚封装等技术进行研究,提出了一种1024×256阵列规模的集成式CCD-CMOS图像传感器。该器件实现了CCD信号的高精度数字化处理、高速输出及多芯粒的技术融合,填补了国内CCD-CMOS三维集成技术空白。测试结果表明:集成CCD-CMOS器件的光响应和成像功能正常,双边成像效果良好,图像无黑条和坏列,互连连通率(99.9%)满足三维集成要求,实现了集成式探测器件的大满阱高灵敏度成像(满阱电子数达165.28ke-、峰值量子效率达86.1%)、高精度数字化(12bit)和高速输出(行频率达100.85kHz),满足集成化、数字化、小型化的多光谱探测成像系统要求。