CMOS电路中抗Latch-up的保护环结构研究

闩锁是CMOS集成电路中的一种寄生效应,这种PNPN结构一旦被触发,从电源到地会产生大电流,导致整个芯片的失效。针对芯片在实际测试中发现的闩锁问题,介绍了闩锁的测试方法,并且利用软件Tsuprem4和Medici模拟整个失效过程,在对2类保护环(多子环/少子环)作用的分析,以及各种保护结构的模拟基础之上,通过对比触发电压和电流,得到一种最优的抗Latch up版图设计方法,通过进一步的流片、测试,解决了芯片中的闩锁失效问题,验证了这种结构的有效性。     

Determining stress intensity factors of composites using crack opening displacement

The main purpose of this paper is to find the mixed-mode stress intensity factors of composite materials using the crack opening displacement (COD). First, a series solution of the composite material with a crack was used to evaluate COD values. Then, the least-squares method was used to calculate mixed-mode stress intensity factors. This algorithm can be applied to any method that generates or measures COD values. The major advantage of this method is that COD values very near the crack tip are not necessary. Both finite element simulations and laboratory experiments were applied to validate this least-squares method with acceptable accuracy if the even terms of the series solution are removed.     

Threshold‐Based Camera Motion Characterization of MPEG Video

We propose an efficient scheme for camera motion characterization in MPEG‐compressed video. The proposed scheme detects six types of basic camera motions through threshold‐based qualitative interpretation, in which fixed thresholds are applied to motion model parameters estimated from MPEG motion vectors (MVs). The efficiency and robustness of the scheme are validated by the experiment with real compressed video sequences.     

On the Realization of Current－Mode Continuous－Time Operational Transconductance Capacitance Filter

ＯｎｔｈｅＲｅａｌｉｚａｔｉｏｎｏｆＣｕｒｒｅｎｔ－ＭｏｄｅＣｏｎｔｉｎｕｏｕｓＴｉｍｅＯｐｅｒａｔｉｏｎａｌＴｒａｎｓｃｏｎｄｕｃｔａｎｃｅＣａｐａｃｉｔａｎｃｅＦｉｌｔｅｒ￥ＧｕｏＪｉｎｇｂｏａｎｄＨａｎＱｉｎｇｑｕａｎ（ＣｈａｎｇｃｈｕｎＰｏｓ...     

全耗尽CMOS／SOI技术的研究进展

ＳＯＩ材料技术的成熟，为功耗低，抗干扰能力强，集成度高，速度快的ＣＭＯＳ／ＳＯＩ器件的研制提供了条件，分析比较了ＣＭＯＳ／ＳＯＩ器件与体硅器件的差异，介绍了国外薄膜全耗尽ＳＯＩ技术的发展和北京大学微电子所的研究成果。     

Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity

To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown.     

Low-Power Adaptive Biased Integrated Amplifiers

In this paper the author will present the working principle and the applications of a novel adaptive biasing topology, designed to decrease the stand-by power dissipation without affecting the transient performance of low-power amplifiers. The proposed circuit, whose principle and circuit topology can be implemented both in CMOS and in bipolar standard technologies, gives a biasing current whose value depends on the applied input differential voltage and can be set according to the requested transient performance constraints. The adaptive architecture can be utilized in the design of high-efficient low-power operational amplifiers, for the biasing of both the input stage (where the input source current is dynamically increased) and the output stage (where the output current can be controlled and limited). These amplifiers show a very good behaviour, evaluated in terms of two efficiency factors, if compared with those of other adaptive solutions and class-AB topologies, proposed in the literature. Simulation results and also measurements on a chip prototype, fabricated in a standard CMOS technology, are finally presented.     

混合集成型光学拾音器的设计与制作

通过混合集成型结构光学拾音器的光学设计和芯片设计，制作了包含微光学棱镜，光电探测器和信号放大电路的混合集成型光学拾音器。经过测试，发现有较好的信号输出特性，表明混合集成型光学拾音器已基本研制成功。     

2.5Gb/s和3.125Gb/s速率级0.35μmCMOS限幅放大器

采用了TSMC0.35μm CMOS工艺实现了可用于SONET/SDH2.5Gb/s和3.125Gb/s速率级光纤通信系统的限幅放大器。通过在芯片测试其最小输入动态范围可达8mVp—p，单端输出摆幅为400mVp-p，功耗250mW，含信号丢失检测功能，可以满足商用化光纤通信系统的使用标准。