二维C/SiC复合材料在冲击拉伸下的损伤过程

利用分离式霍普金森拉杆实验装置(SHTB)和超高速照相机,对二维C/SiC复合材料进行了冲击拉伸力学性能实验研究,同时结合其宏观力学行为,分析了在冲击拉伸载荷作用下的损伤破坏过程。结果表明:材料的应力-应变曲线呈明显的非线性特征,其内部损伤破坏和裂纹扩展过程分为四个阶段:损伤积累于第一阶段,裂纹起源于第二阶段,屈服失效于第三个阶段,快速扩展于第四个阶段。     

近场气泡载荷下柔性结构耦合响应实验研究

通过电火花气泡装置和高速摄像设备对气泡与附近刚性/柔性边界间的耦合现象进行实验观测和研究。针对不同材质平板和不同距离参数下气泡脉动实验数据进行整理,对气泡动力学特性如撕裂现象、射流方向特性及气泡迁移特性等进行机理分析;并借助MATLAB开发图片数字化识别程序,分析总结了整个气泡脉动载荷下柔性板的整体运动响应模式和结构中心测点的响应特征。实验结果表明:气泡在柔性板附近收缩时出现“棒槌”状或气泡撕裂及远离对向射流现象;探究气泡载荷下柔性结构响应模式,发现气泡膨胀时柔性板呈一阶响应,收缩时呈现三阶响应及双峰值迁移现象。     

Real-Time Recognition and Location of Indoor Objects

Object recognition and location has always been one of the research hotspots in machine vision. It is of great value and significance to the development and application of current service robots, industrial automation, unmanned driving and other fields. In order to realize the real-time recognition and location of indoor scene objects, this article proposes an improved YOLOv3 neural network model, which combines densely connected networks and residual networks to construct a new YOLOv3 backbone network, which is applied to the detection and recognition of objects in indoor scenes. In this article, RealSense D415 RGB-D camera is used to obtain the RGB map and depth map, the actual distance value is calculated after each pixel in the scene image is mapped to the real scene. Experiment results proved that the detection and recognition accuracy and real-time performance by the new network are obviously improved compared with the previous YOLOV3 neural network model in the same scene. More objects can be detected after the improvement of network which cannot be detected with the YOLOv3 network before the improvement. The running time of objects detection and recognition is reduced to less than half of the original. This improved network has a certain reference value for practical engineering application.     

基于高速摄影技术模拟深水爆破环境下气泡脉动规律研究

采用GX-8高速摄影机在水下爆炸罐中进行0.8².4gTNT当量炸药爆炸试验监测,运用注水加压方式在模拟深水环境中实拍出气泡脉动过程。分析气泡半径、脉动周期与药量、水深之间的关系得到:脉动周期和同一周期内最大脉动半径随着水深的增加呈对数衰减趋势;同一水深条件下最大脉动半径随药量增加明显增大,且脉动周期随之增加。将实测结果与经验公式计算值进行比较,验证了库尔公式在深水环境下的适用性。     

基于CM O S 图像传感器的以太网传输系统设计

CMOS image sensor has been widely used in the field of visible image. It has the characteristics of low cost, low power consumption and high integration. How to transmit the collected image data effectively and improve the transmission distance is one of the main problems in practical application. In addition to the advantages of providing long-distance transmission, Ethernet has the characteristics of high transmission efficiency, simple structure and reliable operation. This paper describes a design scheme of Ether- net transmission system based on CMOS image sensor. Image data is collected by CMOS image sensor, image processing is realized by FPGA, and transmission is carried out through Ethernet interface. The method of displaying image on PC meets the application requirements of the design.     

Negative capacitance independent multi-gate FinFETs and their optimisations

In order to reduce the operating voltage of FinFET and increase the flexibility of integrated circuit design, we have proposed a Negative Capacitance Independent Multi-Gate FinFET (NC-IMG-FinFET) with Ferroelectric-Metal-Insulator-Semiconductor-Insulator (FMISI) structure. Both the device and circuit analysis model of NC-IMG-FinFET are addressed, which are used to analyse the performance parameters of the device (the surface potential, internal gate voltage amplification, Sub-threshold Swing (SS), on-current and leakage) and the performance of a circuit (delay, power consumption, power delay product (PDP)). The simulation model of the NC-IMG-FinFET has been constructed by combining BSIM-IMG model with ferroelectric Landau-Khalatnikov model. The optimisations for ferroelectric film thickness of the NC-IMG-FinFETs are carried out in terms of device characteristics and circuit performances. The simulation results are consistent with the analysis results, indicating that the NC-IMG-FinFET has superior performance compared with the baseline device, in terms of smaller leakage, larger on/off current ratio and smaller SS (38.3 mV/dec at room temperature). Compared with the baseline IMG-FinFET circuits, there is large performance improvement for the NC-IMG-FinFET circuits, in terms of the power consumption and PDP.     

Fast locking,startup-circuit free,low area, 32-phase analog DLL

This work presents 32-phase analog delay-locked-loop (DLL) having fast locking ability, startup-circuit free operation, and a low area with improved DNL-INL performance. The proposed faster delay-cell and the new bias-circuit enable startup-circuit free operation under process-voltage-temperature (PVT) variation, while the DLL achieves low area and faster locking by using a small filter capacitor. Again, input and output clocks pass through the respective CMOS buffer before the phase detector (PD) for load matching, which reduces DNL-INL in the DLL. The analog DLL locks in less than 54 or 56 clock cycles depending upon initial control voltage (supply or ground voltage) with 100 MHz input clock. The DLL generates 32-phase clocks with a bin-size of 312.5 ps, the peak-to-peak period jitter of 9.51 ps, the rms period jitter of 1.36 ps, the phase-offset error of 4.72 ps, DNL and INL less than ±0.11 LSB. The design consumes 3.54 mW power with a supply voltage of 3.3 V, and an area of 0.017 mm² in UMC 180 nm MMRF technology. ^© 2001 Elsevier Science. All rights reserved     

Ultra-low power m-sequence code generator for body sensor node applications

In this paper, a design of low power m-sequence code generator is proposed. The efficiency of producing the code sequence within the region of sub-threshold voltage is investigated using 90 nm technology and verified using the auto-correlation and eye diagram characterizations. A further method of power saving in addition to voltage reduction is carried out by scaling the technology node from 90 to 65 nm. A comparison of power consumption and maximum attainable frequency between both technologies is performed. The ratio of power saving while using 65 nm technology is ranging from 45% to 55% for the three different code lengths investigated.     

基于图像检测技术的室内人员服装热阻测量研究

目前服装热阻主要采用人工问卷调查的方式测量,需要受试者多次填写问卷,估计过程复杂且不易实时测量,而且传统估计方法只对静态热阻做预测,没有考虑人员运动状态、室内风速的影响。图像检测方面,基于Mask RCNN网络的服装检测方法存在多尺度特征信息丢失、融合不佳等问题。针对这些情况,提出一种改进的Mask RCNN服装检测网络方法,应用并实现室内人员动态服装热阻的系统设计。首先,通过CCD相机进行图像采集,经过改进的Mask RCNN网络检测着衣量。然后,查表映射法对室内服装热阻进行初步估计。最后,利用测量仪器测得风速、行走速度对服装热阻修正,得到动态服装热阻估计结果。实验结果表明,改进的Mask RCNN网络平均识别精度比原方法提高了1.1%,在动态服装热阻估计方面,与传统方法相比,能修正0.13的平均偏差。     

Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits

By the reduction in the size of transistors and the development of submicron technology, as well as the construction of more integrated circuits on chips, leakage power has become one of the main concerns of electronic circuit designers. In this article, we first review techniques presented in recent years to reduce leakage power and then present a new technique based on the gate-level body biasing technique and the multi-threshold CMOS technique to minimize leakage power in digital circuits. Afterward, we develop another new method by improving the first proposed technique to achieve higher efficiency and simultaneously reduce leakage power and propagation delay in digital circuits. In the proposed technique, we use two dynamic threshold MOSFET transistors to reduce leakage current. In this paper, the body biasing generator structure is applied to reduce propagation delay. The proposed technique has been successfully validated and verified by post-layout simulation with Cadence Virtuoso based on the 32 nm process technology.We evaluate the efficiency of the proposed techniques by examining factors including power, delay, area, and the power delay product. The simulation results using HSPICE software and performance analysis to process corner variations based on the 32 nm process technology show that the proposed technique, in addition to having proper performance in different corners of the technology, significantly reduces leakage power and propagation delay in logic CMOS circuits. In general, the proposed technique has a very successful performance compared to previous techniques.