关注区可变的实时仿真方法与平台

交直流混合电网的实时仿真既要考虑电力电子设备的开关特性,又要保证适应较大的电网规模,在实际工程中面临诸多困难.给子网络赋予动态可变的关注标志,对关注子网络采用存储压力小的节点消去法,对非关注子网络采用计算量少的线性组合法,从而保证骨架型节点电压法的实用性.在Xilinx公司的Virtex-7 FPGA VC709开发板中,采用无缝的并行化仿真计算程序对接方式和灵活的结构参数查询方法解决了现场可编程逻辑门阵列资源的紧缺问题,设计了一种关注区可变的实时数字仿真平台.以典型的交直流混合电网为例,仿真验证了所提方法的可行性与所研发平台的有效性.     

CPLD/FPGA在工件取放设备中的应用

在分析PLC优缺点的基础上，提出一种利用在线可编程逻辑控制代替PLC的新技术。此外，给出了用在线可编程器件CPLD/FPGA组成的、VHDL语言实现的工件取放设备控制电路设计和程序。     

Janus II: A new generation application-driven computer for spin-system simulations

This paper describes the architecture, the development and the implementation of Janus II, a new generation application-driven number cruncher optimized for Monte Carlo simulations of spin systems (mainly spin glasses). This domain of computational physics is a recognized grand challenge of high-performance computing: the resources necessary to study in detail theoretical models that can make contact with experimental data are by far beyond those available using commodity computer systems. On the other hand, several specific features of the associated algorithms suggest that unconventional computer architectures–that can be implemented with available electronics technologies–may lead to order of magnitude increases in performance, reducing to acceptable values on human scales the time needed to carry out simulation campaigns that would take centuries on commercially available machines. Janus II is one such machine, recently developed and commissioned, that builds upon and improves on the successful JANUS machine, which has been used for physics since 2008 and is still in operation today. This paper describes in detail the motivations behind the project, the computational requirements, the architecture and the implementation of this new machine and compares its expected performances with those of currently available commercial systems.     

一种基于多核嵌入式系统的TD-LTE同步校正方法

针对TD-LTE系统中同步性错误随机发生的问题,提出了一种通过ARM+DSP+FPGA平台的嵌入式系统实现帧号和原语的同步校正方法。该方法基于TD-LTE射频一致性测试仪表硬件平台,通过该嵌入式系统中ARM、DSP、FPGA间的协调工作,由GPMC模块通过帧号和原语两方面对系统同步性进行校正。在TD-LTE射频一致性测试仪表硬件平台中进行了验证,结果表明,该方法在实现帧号与子帧号同步校正的基础上明显提高了TD-LTE系统通信的稳定性。     

基于硬件Kalman滤波器的航拍云台姿态获取

航拍云台姿态获取是航空摄影中相机姿态校正的基本依据,介绍了一种基于硬件Kalman滤波器的航拍云台姿态获取的实现方法。设计中采用MPU6050作为系统的姿态传感器,它提供三轴角速度和三轴加速度数据。根据系统特征建立Kalman滤波方程对这些数据进行数据融合处理,Kalman滤波过程中的加减乘除浮点数运算由FPGA实现,外部数据的采集和时序的控制也由FPGA完成。经过对实际数据的处理实验,得出该硬件模块可以获得较为准确的航拍云台姿态,输出结果误差在-1.5°~1.5°范围内。     

相控阵雷达天线阵面记录回放系统

相控阵雷达广泛应用,其天线阵面对记录回放系统的数据速率要求提升。针对两种传统记录回放系统架构的不足,结合其优点,设计并实现了一种新型的基于FPGA的记录回放系统。该系统设计为板卡的形式,FPGA实现对硬盘的读写操作,采用自定义的文件系统对数据进行管理。经过测试,系统记录速度可以达到292 MB/s,回放速率为340 MB/s。实验结果表明,该记录回放系统性能稳定,通用性好,存储速率满足要求。     

基于FPGA的高速数据存储系统优化设计

针对遥测系统数据记录装置中数据传输速率与存储速率不匹配的问题,提出Flash的并行存储方案,采用交替双平面的编程方式可以使得存储器的存储速率达到单片Flash最高存储速率的2倍,即60 MB/s;对控制单元FPGA内部双端口RAM的逻辑设计进行改进,解决了数据存储异常的现象。在数据回收方面,提出了多备份的设计思想和备用读数接口的设计方案,已在工程应用中得到成功实践,验证了该数据记录装置的可靠性。     

基于FPGA的高频全数字低电平系统算法实现

本套加速器高频低电平系统(LLRF)是中国ADS注入器II高频系统的原型机,其工作频率为162.5 MHz,以实现超导加速腔的幅度与相位稳定控制和谐振频率调节。该系统主要由射频前端和数字信号处理FPGA两部分组成。射频前端主要实现高频信号的上下变频和电平匹配;数字信号处理FPGA是系统的核心,主要完成射频信号幅值与相位的数字稳定控制,超导腔谐振频率控制,以及1 000 M以太网通信。在实验室环境下,对该系统进行了幅度和相位稳定度测试,相位稳定度峰峰值为±0.3°,有效值为0.09°,幅值相对稳定度峰峰值为±5×10-3,有效值为3.2×10-3,达到了设计要求。     

PMSS: A programmable memory system and scheduler for complex memory patterns

HPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. However, applications are getting more complex, with multiple kernels and complex data arrangements, generating overhead while scheduling/managing system resources. Due to this reason all classes of multi threaded machines–minicomputer to supercomputer–require to have efficient hardware scheduler and memory manager that improves the effective bandwidth and latency of the DRAM main memory. This architecture could be a very competitive choice for supercomputing systems that meets the demand of parallelism for HPC benchmarks. In this article, we proposed a Programmable Memory System and Scheduler (PMSS), which provides high speed complex data access pattern to the multi threaded architecture. This proposed PMSS system is implemented and tested on a Xilinx ML505 evaluation FPGA board. The performance of the system is compared with a microprocessor based system that has been integrated with the Xilkernel operating system. Results show that the modified PMSS based multi-accelerator system consumes 50% less hardware resources, 32% less on-chip power and achieves approximately a 19x speedup compared to the MicroBlaze based system.     

基于CY7C68013A的USB2.0高速接口设计

为了充分利用USB2.0的带宽,解决数据传输时存在的速度瓶颈问题,提出了一种基于CY7C68013A的USB2.0高速接口设计方法。采用CY7C68013A的SLAVE FIFO工作模式,芯片内部CPU不参与数据传输,FPGA设计的外部控制电路直接读写芯片内部FIFO,有效避免了内部CPU参与数据传输时带来的时间开销,从而提高了传输速度。