非零速启停的低功耗步进电机控制器研究

为了优化步进电机开环控制性能,对非零速启停的加减速曲线算法及其低功耗硬件逻辑实现进行了研究。针对零速启停的加减速曲线存在控制性能难以充分发挥的问题,提出了一种非零速启停的步进电机线性加减速曲线算法,将加减速过程划分为四种转动模式,可构建任意的线性速度剖面。首先理论推导了四种加减速转动模式的控制脉冲周期;其次结合流水线设计思想优化加减速曲线算法的硬件逻辑模型,在FPGA中设计了步进电机控制器IP核,并采用门控时钟等低功耗IC设计技术实现了IP核的低功耗;最后,搭建了实验平台进行验证。实验结果表明,IP核可以实现四种转动模式的非零速启停控制,实现了高实时、高精度驱动,提升了20%的控制性能,电路面积优化约30%,功耗降低53%,验证了方案的可行性与有效性。     

OCEAN,a flexible adaptive Network-On-Chip for dynamic applications

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement of applicatives tasks in reconfigurable zones. However, the dynamic management of the tasks impacts the communications since they are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various interconnection networks are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the OCEAN network that supports the communication constraints into the context of dynamic reconfigurations. Thanks to a generic platform allowing in situ characterizations of network performances, fair comparisons of various Networks-On-Chip can be realized. The FPGA and ASICs implementations of the OCEAN network are also discussed.     

FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards

Performance evaluation of parallel software and architectural exploration of innovative hardware support face a common challenge with emerging manycore platforms: they are limited by the slow running time and the low accuracy of software simulators. Manycore FPGA prototypes are difficult to build, but they offer great rewards. Software running on such prototypes runs orders of magnitude faster than current simulators. Moreover, researchers gain significant architectural insight during the modeling process. We use the Formic FPGA prototyping board [1], which specifically targets scalable and cost-efficient multi-board prototyping, to build and test a 64-board model of a 512-core, MicroBlaze-based, non-coherent hardware prototype with a full network-on-chip in a 3D-mesh topology. We expand the hardware architecture to include the ARM Versatile Express platforms and build a 520-core heterogeneous prototype of 8 Cortex-A9 cores and 512 MicroBlaze cores. We then develop an MPI library for the prototype and evaluate it extensively using several bare-metal and MPI benchmarks. We find that our processor prototype is highly scalable, models faithfully single-chip multicore architectures, and is a very efficient platform for parallel programming research, being 50,000 times faster than software simulation.     

Evaluation of stereo correspondence algorithms and their implementation on FPGA

The accuracy of stereo vision has been considerably improved in the last decade, but real-time stereo matching is still a challenge for embedded systems where the limited resources do not permit fast operation of sophisticated approaches. This work presents an evaluation of area-based algorithms used for calculating distance in stereoscopic vision systems, their hardware architectures for implementation on FPGA and the cost of their accuracies in terms of FPGA hardware resources. The results show the trade-off between the quality of such maps and the hardware resources which each solution demands, so they serve as a guide for implementing stereo correspondence algorithms in real-time processing systems.     

基于MPC8270的多总线处理器模块设计

介绍了一款基于MPC8270的PowerPC处理器模块设计方法,以目前应用广泛的RISC微处理器MPC8270作为核心处理器,以FPGA为控制核心电路,实现百兆以太网、USB 2.0、RS422和CPCI多种总线功能,提供日历时钟功能,采用VxWorks作为操作系统,性能稳定可靠。     

基于MAX+PLUSII模块化设计的智力竞赛抢答器

设计了一款造价低,体积小,操作简单,适用性广的抢答器。该抢答器是基于MAX+PLUSII软件,在FPGA芯片上设计的,可实现多人智力竞赛抢答。     

激光遥感图像高速滤波器算法的FPGA实现

针对激光遥感信号高速高精度的要求,利用FPGA的多任务、高速并行性设计系统进行滤波。考虑到激光光电传感器设计的滤波器会有很大的信号衰减,且具有精度要求高的特点,提出了基于 FPGA内部基本逻辑单元、乘法器、存储器,经过乘法分解和时序设计,实现具有可移植性的图像高速分辨的方法。系统采用FPGA设计平台,并用Verilog语言设计程序。试验结果验证,该滤波器对激光遥感信号具有高速、精确滤波功能,同时表明利用低端FPGA设计激光滤波器必将成为未来发展趋势。     

基于FPGA的声呐信号数字预处理机的设计

介绍了一种基于单片FPGA的声呐信号数字预处理机设计方案。系统可以对30路换能器输出的模拟信号进行同步采样,采样数据在FPGA中依次进行正交解调、FIR滤波、波束形成等声呐信号预处理计算,减轻了上位机计算任务,解决了多阵元声呐设备中数据采集速度和数据处理速度难以匹配的瓶颈。     

MUSIC算法的FPGA实现

针对多重信号分类（MUSIC）算法计算复杂度高,难以实时实现的特点,给出了适用于均匀线阵的实数化预处理算法和实用的空间谱定义,并选择了适合FPGA硬件实现的特征值分解算法,给出了MUSIC算法FPGA实现的整体架构。仿真实验结果表明,该FPGA实现能够完成MUSIC算法的准确、快速计算。     

基于FPGA的高速数据转存系统

SAR雷达前端数据采集系统速度与存储系统容量的日益提高,对数据转存系统的性能提出了更高的要求以Xilinx公司Virtex-5系列FPGA为硬件平台,基于PCI—E协议与Aurora协议提出了一种高速数据转存系统解决方案．在Aurora协议基础之上,自定义了一种可靠的帧格式;利用双口RAM对数据进行缓存,以乒乓方式操作,确保了在输入、输出数据传输速率不匹配情况下数据传输的稳定性与可靠性：转存系统与PC通过PCI-E总线进行通信,命令交互采用PIO模式,图像与列表数据传输采用DMA模式．经实际测试,该方案能够满足某型号SAR雷达系统对高速数据转存的要求．