中国传统建筑门的形态研究

中国古建筑的门,不仅仅只是一种建筑形态,而且是人们心目中的一个重要概念。因为概念与原型之间的互动,在有关门的具体的建筑活动中,这些形而上的观念又不断显露并发展,促进着门本身在艺术上的进步。文章从文化和心理方面等多方面对中国古建筑的门进行了分析研究。     

When do extra majority gates help? Polylog (N) majority gates are equivalent to one

Suppose that a Boolean functionf is computed by a constant depth circuit with 2 ^m AND-, OR-, and NOT-gates—andm majority-gates. We prove thatf is computed by a constant depth circuit with AND-, OR-, and NOT-gates—and a single majority-gate, which is at the root.One consequence is that if a Boolean functionf is computed by an AC⁰ circuit plus polylog majority-gates, thenf is computed by a probabilistic perceptron having polylog order. Another consequence is that iff agrees with the parity function on three-fourths of all inputs, thenf cannot be computed by a constant depth circuit with AND-, OR-, and NOT-gates, and majority-gates.     

A variable-precision square root implementation for field programmable gate arrays

Applications requiring variable-precision arithmetic often rely on software implementations because custom hardware is either unavailable or too costly to build. By using the flexibility of the Xilinx XC4010 field programmable gate arrays, we present a hardware implementation of square root that is easily tailored to any desired precision. Our design consists of three types of modules: a control logic module, a data path module to extend the precision in 4-bit increments, and an interface module to span multiple chips. Our data path design avoids the common problem of large fan-out delay in the critical path. Cycle time is independent of precision, and operation latency can be independent of interchip communication delays.Notation S_j square root digit of weight 2^–j - S _j {–1, 0, 1} - S[j] computed square root value as of stepj - S _j ^s sign bit in the representation ofS _j in sign and magnitude form - S _j ^m magnitude bit in the representation ofS _j in sign and magnitude form - w[j] residual at stepj in two's complement carry-save representation - a sum vector in the carry-save representation of 2w[j] - b carry vector in the carry-save representation of 2w[j] - a _i bit of weight 2^–i in the sum vector,a - b_i bit of weight 2^–i in the carry vector,b - T[j]=–S[j – 1]s_j – s _j ² 2^–(j+1) T _i bit of weight 2^–i inT     

Ultraviolet photodetectors and readout based on a-IGZO semiconductor technology

In this work, real-time ultraviolet photodetectors are realized through metal–semiconductor–metal (MSM) structures. Amorphous indium gallium zinc oxide (a-IGZO) is used as semiconductor material and gold as metal electrodes. The readout of an individual sensor is implemented by a transimpedance amplifier (TIA) consisting of an all-enhancement a-IGZO thin-film transistor (TFT) operational amplifier and a switched capacitor (SC) as feedback resistance. The photosensor and the transimpedance amplifier are both manufactured on glass substrates. The measured photosensor possesses a high responsivity R , a low response time t _{R E S} , and a good noise equivalent power value NEP .     

基于Attention-CGRU网络的中文语音情感识别

正确识别语音中包含的情感信息可以大幅提高人机交互的效率.目前,语音情感识别系统主要由语音特征抽取和语音特征分类两步组成.为了提高语音情感识别准确率,选用语谱图而非传统声学特征作为模型输入,采用基于attention机制的CGRU网络提取语谱图中包含的频域信息和时域信息.实验结果表明:在模型中引入注意力机制有利于减少冗余信息的干扰,并且相较于基于LSTM网络的模型,采用GRU网络的模型预测精确度更高,且在训练时收敛更快,与基于LSTM的基线模型相比,基于GRU网络的模型训练时长只有前者的60%.     

基于FPGA的高性能可编程数据平面研究综述

可编程数据平面(PDP)一方面支持网络应用的卸载与加速, 给网络应用带来了革命性的发展机遇; 另一方面支持新协议、新服务的快速实现和部署, 促进了网络创新和演进, 是近年来网络领域的研究热点. FPGA因其通用的计算架构、丰富的片内资源和扩展接口提供了多种可编程数据平面的具体实现, 支持更广范围的应用场景. 同时, FPGA还为探索更通用的可编程数据平面抽象提供了可能. 因此, 基于FPGA的可编程数据平面受到了学术界与产业界的广泛关注. 首先分类别阐述基于FPGA的可编程数据平面(F-PDP)抽象. 接着, 介绍基于F-PDP快速构建网络应用的关键技术的研究进展. 之后, 介绍基于F-PDP的新型可编程网络设备. 此外, 从提升网络性能、构建网络测量框架以及部署网络安全应用这3个方面, 详细梳理近年来基于F-PDP的应用研究成果. 最后, 探讨F-PDP未来可能的研究趋势.     

Wireless measurement of Float-Sink motion of Variously-shaped objects in Gas-Solid fluidized bed

The float-sink motions of coarse objects in a gas–solid fluidized bed were investigated experimentally using a newly developed wireless sensor system. The Lagrangian sensor system developed by our previous study, which can measure the vertical position of a freely-moving object in an invisible system, was extended to measure the attitude angle and vertical position of variously-shaped objects simultaneously. The vertical motion of objects which have different shapes with the same mass and volume was measured using the Lagrangian sensor under the density conditions similar to the apparent density of the fluidized bed. The results demonstrate that the float-sink motions of objects in the gas–solid fluidized bed differ significantly depending on the shape of the object, even at the same density, in contrast to those in water. It was found that non-spherical objects tend to float more easily than spherical objects, which supports the numerical results shown in our previous study (Tsuji et al., Chem. Eng. Sci., 2022). Simultaneous measurement of the position and attitude angle highlights the importance of the angular motion of objects in terms of the float-sink motion. The interaction of the object with the media particles in the fluidized bed differs depending on the object shape, which indicates that each shape involves a unique float-sink mechanism.     

高速脉冲信号源的设计与实现

高速脉冲信号源是数据采集系统的重要组成部分,常用于系统的自检与测试中.根据实际要求,提出了高速运放调理和高速电子开关两种方案.分别对高速运放、信号幅值调理、驱动电路和高速电子开关的选择进行了研究,给出了具体的硬件电路设计.并结合相关理论,分析了信号在传输过程中出现的反射现象,提出了符合要求的解决方案.此高速脉冲信号源已成功应用于某采集设备的自检和测试中,效果良好.     

一种基于TDC的相对频差测量方法

提出了一种基于时间/数字转换器( TDC)的频率差测量方法.该方法使用延迟链和参考时钟结合的TDC直接数字量化频率差.测量系统与非线性标定模块均在现场可编程门阵列( FPGA)中实现.为了对频率差检测精度进行评估,使用振荡器作为仿真输入信号进行了实验.结果显示:所提出的测量方法对ΔF/F的测量噪声可以达到1 ×10-8/ 槡Hz.在实验结果的基础上,对测量噪声的来源进行了分析.     

基于不同排序方法的快速霍夫曼编码硬件实现

针对软件霍夫曼静态编码计算量大,而动态霍夫曼编码使得解码器同样复杂的缺点,提出了一种准动态霍夫曼硬件编码器。该编码器每次对一组数据序列进行静态编码,然后将编码并行输出,从而使得编码器具有较高的编码速度,而其延迟时间仅为一次编码过程的总时间。首先,为了充分利用硬件并行特性,分别使用动态排序和静态排序两种排序网络,以适应不同场合的编码需要。然后,使用数据流驱动的硬件二叉树构建和解析结构得到信源符号对应的霍夫曼编码。最后,将储存在FIFO中的输入数据查表并输出。设计结果表明,当使用Nexys4 DDR平台时,该编码器可以工作于100MHz以上的频率,同时具有吞吐高、延迟低、编码效率高和译码器简单的特性。