氮化镓干法刻蚀研究进展

对比了RIE,ECR,ICP等几种GaN干法刻蚀方法的特点.回顾了GaN干法刻蚀领域的研究进展.以ICP刻蚀GaN和AlGaN材料为例,通过工艺参数的优化,得到了高刻蚀速率和理想的选择比及形貌.在优化后的刻蚀工艺条件下GaN材料刻蚀速率达到340nm/min,侧墙倾斜度大于80°且刻蚀表面均方根粗糙度小于3nm.对引起干法刻蚀损伤的因素进行了讨论,并介绍了几种减小刻蚀损伤的方法.     

Si基GaN薄膜的制备方法及结构表征

分别采用射频磁控溅射、热壁化学气相沉积(CVD)、电泳沉积法制备GaN薄膜。利用扫描电镜(SEM)、荧光光谱仪对样品进行结构、形貌和发光特性的分析比较。射频磁控溅射方法中,把SiC中间层沉淀到Si衬底上,目的是为了缓冲由GaN外延层和Si衬底的晶格失配造成的应力。结果证实了SiC中间层提高了GaN薄膜的质量。热壁化学气相沉积法制备GaN晶体膜时,选择H2作反应气体兼载体,有利于GaN膜的形成。电泳沉积法显示所得样品为六方纤锌矿结构的GaN多晶薄膜。结果表明:溅射法制备的GaN薄膜结晶效果好;CVD法制备时GaN薄膜应用范围广;电泳沉积法操作方便、简单易行。     

Si(111)衬底上GaN外延材料的应力分析

对Si(111)衬底上GaN外延材料的应力随着低温AlN插入层数的变化进行了分析研究。通过喇曼散射谱在高频E2(TO)模式下的测试分析发现,随着低温AlN插入层数的增加,GaN材料的E2(TO)峰位逐渐接近体GaN材料的E2(TO)峰位(无应力体GaN材料的E2(TO)峰位为568cm-1),计算得出GaN材料的应力从1.09GPa减小到0.42GPa。同时,使用室温光荧光谱进行了分析验证。结果表明,Si衬底上GaN外延材料受到的是张应力,通过低温AlN插入层技术可以有效降低GaN材料的应力,并且最终实现了表面光亮的厚层无裂纹GaN材料。     

The influence of 1 nm AlN interlayer on properties of the Al0.3Ga0.7N/AlN/GaN HEMT structure

The sheet carrier concentrations, conduction band profiles and amount of free carriers in the barriers have been determined by solving coupled Schrödinger and Poisson equation self-consistently for coherently grown Al_0.3Ga_0.7N/GaN and Al_0.3Ga_0.7N/AlN/GaN structures on thick GaN. The Al_0.3Ga_0.7N/GaN heterojunction structures with and without 1 nm AlN interlayer have been grown by MOCVD on sapphire substrate, the physical properties for these two structures have been investigated by various instruments such as Hall measurement and X-ray diffraction. By comparison of the theoretical and experimental results, we demonstrate that the sheet carrier concentration and the electrons mobility would be improved by the introduction of an AlN interlayer for Al_0.3Ga_0.7N/GaN structure. Mechanisms for the increasing of the sheet carrier concentration and the electrons mobility will be discussed in this paper.     

Efficiency droop behavior of GaN-based light emitting diodes under reverse-current and high-temperature stress

The efficiency droop behavior of GaN-based light emitting diodes (LEDs) is studied when the LEDs are under reverse-current and high-temperature stress tests respectively. It is found that reverse-current stress mainly induces additional non-radiative recombination centers within the active region of InGaN/GaN multiple quantum wells, which degrade the overall efficiency of the GaN LED under test but push the peak-efficiency-current towards higher magnitude. The up-shift of peak-efficiency-current can be explained by a rate-equation model in which the newly-created defects by reverse-current stress enlarge the dominant low-current region of non-radiative recombinations. Comparatively, high-temperature stress mainly increases the series resistance of the LED under test. Although the overall efficiency of the GaN LED also drops, there is no shift of peak-efficiency-current induced by the high-temperature stress.     

Temperature dependence of Al/Ti-based Ohmic contact to GaN devices: HEMT and MOSFET

In this paper two types of Al/Ti-based Ohmic contacts to Gallium Nitride (GaN) based devices are presented; ImplantedN⁺GaN (like the ones found in the Source/Drain of GaN Metal Oxide Semiconductor Field Effect Transistors-MOSFET) and heterojunction (HJ) AlGaN/GaN contacts (Source/Drain of High Electron Mobility Transistors-HEMT). Sheet resistance (R_sh) and contact resistance (R_c) have been investigated in the temperature (T) range of 25-250 °C. It was found that the R_sh (850/700 Ω□) (25/250 °C) and R_c (2.2/0.7 Ωmm) decrease with T for ImplantedN⁺GaN contact and R_sh (400/850 Ω□) and R_c (0.2/0.4 Ωmm) (weakly for R_c) increase with T for HJAlGaN/GaN contact. Numerical computation based models are used to determine the theoretical R_sh and R_c behavior with T and to fit the experimental values.     

"自上而下"法制备高性能GaN纳米线阵列

针对自下而上生长GaN纳米线的尺寸、形态、取向不易控制的问题,文中采用自上而下刻蚀的方法来制备GaN纳米线材料。以图形化的金属Ni作为掩膜对GaN进行ICP刻蚀,系统研究了刻蚀参数,主要是ICP功率以及RF功率对GaN纳米线形貌以及拉曼、PL光谱的影响,同时也对比了干法刻蚀后,有无湿法处理的影响。研究发现,当ICP功率为1 000 W,RF功率为100 W时,GaN纳米线的拉曼和PL光谱强度较大,表明此功率下刻蚀的纳米线损伤较小。经过KOH浸泡30 min后,GaN纳米线的形貌得到了改善,拉曼和PL光谱强度均优于单纯的干法刻蚀,为下一步器件的制备提供了良好的材料基础。     

Surface etching of 6H-SiC (0001) and surface morphology of the subsequently grown GaN via MOCVD

The correlation between surface morphological properties of the GaN epilayers and the surface conditions of 6H-SiC (0001) substrates etched in H₂, C₂H₄/H₂, and HCl/H₂ was studied. Etching 6H-SiC in H₂ produced a high quality surface with steps and terraces, while etching in HCl/H₂ produced either a rough surface with many pits and hillocks or a smooth surface similar to that etched in H₂, depending on the HCl concentration and temperature. The GaN epilayers were subsequently deposited on these etched substrates using either a low temperature GaN or a high temperature AlN buffer layer via MOCVD. The substrate surface defects increased the density and size of the “giant” pinholes (2–4 μm) on GaN epilayers grown on a LT-GaN buffer layer. Small pinholes (<100 nm) were frequently observed on the samples grown on a HT-AlN buffer layer, and their density decreased with the improved surface quality. The non-uniform GaN nucleation caused by substrate surface defects and the slow growth rate of planes of the islands were responsible for the formation of “giant” pinholes, while the small pinholes were believed to be caused by misfit dislocations.     

Local electronic properties of AlGaN/GaN heterostructures probed by scanning capacitance microscopy

Local electronic properties in Al_xGa_1−xN/GaN heterostructure field-effect transistor epitaxial layer structures are probed using scanning capacitance microscopy. Acquisition of scanning capacitance images over a wide range of bias voltages combined with theoretical analysis and numerical simulation allows the presence, detailed nature, and possible structural origins of nanometer- to micronscale inhomogeneities in electronic structure to be elucidated. Substantial lateral variations in local threshold voltages for transistor channel formation are observed, at length scales ranging from submicron to >2 μm, and found to arise primarily from local variations in Al_xGa_1−xN layer thickness. Features in electronic structure are also observed that are consistent with the existence of networks of negatively charged threading edge dislocations, as might be formed at island coalescence boundaries during epitaxial growth. The negative charge associated with these structures appears to lead to local depletion of carriers from the channel in the Al_xGa_1−xN/GaN transistor epitaxial layer structure.     

High-performance and broadband photodetection of bicrystalline(GaN)1-x(ZnO)x solid solution nanowires via crystal defect engineering

Crystal defect engineering is widely used as an effective approach to regulate the optical and opto-electronic properties of semiconductor nanostructures.However,photogenerated electron-hole pair recombination centers caused by structural defects usually lead to the reduction of optoelectronic perfor-mance.In this work,a high-performance photodetector based on(GaN)1-x(ZnO)x solid solution nanowire with bicrystal structure is fabricated and it shows excellent photoresponse to ultraviolet and visible light.The highest responsivity of the photodetector is as high as 60,86 and 43 A/W under the irradiation of 365 nm,532 nm and 650 nm,respectively.The corresponding response time is as fast as 170,320 and 160 ms.Such wide spectral responses can be attributed to various intermediate energy levels induced by the introduction of various structural defects and dopants in the solid solution nanowire.Moreover,the peculiar bicrystal boundary along the axial direction of the nanowire provides two parallel and fast trans-mission channels for photo-generated carriers,reducing the recombination of photo-generated carriers.Our findings provide a valued example using crystal defect engineering to broaden the photoresponse range and improve the photodetector performance and thus can be extended to other material systems for various optoelectronic applications.