Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor

This paper reports on the effects of the Halo structure variations on threshold voltage (V_th) in a 22 nm gate length high-k/metal gate planar NMOS transistor. Since the V_th is one of the important physical parameter for determining the functionality of complementary metal-oxide–semiconductor device, this experiment will focus on finding the best combination on process parameter to achieve the best value of V_th. The Halo structure variable process parameters are the Halo implantation dose, the Halo implantation tilting angle, the Source/Drain implantation dose and the compensation implantation dose. The design of the planar device consists of a combination of high permittivity material (high-k) and a metal gate. Titanium dioxide was used as the high-k material instead of the traditional SiO₂ dielectric and tungsten silicide was used as the metal gate. The optimization process was executed using Taguchi's L₉ array to obtain a robust design. Taguchi's Nominal-the-Best signal-to-noise ratio was used in an effort to minimize the variance of V_th. The results show that the V_th values have least variance and the mean value can be adjusted to 0.289 V±12.7% which is in line with projections made by the International Technology Roadmap for Semiconductors.     

Microstructure,optical and electrical properties of sputtered HfTiO high-k gate dielectric thin films

The microstructure, optical and electrical properties of HfTiO high-k gate dielectric thin films deposited on Si substrate and quartz substrate by RF magnetron sputtering have been investigated. Based on analysis from x-ray diffraction (XRD) measurements, it has been found that the as-deposited HfTiO films remain amorphous regardless of the working gas pressure. Meanwhile, combined with characterization of ultraviolet-visible spectroscopy (UV–vis) and spectroscopy ellipsometry (SE), the deposition rate, band gap and optical properties of sputtered HfTiO gate dielectrics were determined. Besides, by means of the characteristic curves of high frequency capacitance–voltage (C–V) and leakage current density–voltage (J–V), the electrical parameters, such as permittivity, total positive charge density, border trap charge density, and leakage current density, have been obtained. The leakage current mechanisms are also discussed. The energy band gap of 3.70 eV, leakage current density of 1.39×10⁻⁵ A/cm² at bias voltage of 2 V, and total positive charge density and border trap charge density of 9.16×10¹¹ cm⁻² and 1.3×10¹¹ cm⁻², respectively render HfTiO thin films deposited at 0.6 Pa, potential high-k gate dielectrics in future CMOS devices.     

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (T_Fin/W_Fin) equal to 1. The nano-stacked high-k Al₂O₃ dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high I_on/I_off ratio > 10⁵ and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.     

Characterization of ZrO2 thin films deposited by MOCVD for high-density 3D capacitors

This work deals with high-density integrated capacitors for output filters in future micro DC–DC converters. To reach high capacitance density, 3D structures were created in silicon with DRIE followed by MOCVD of ZrO₂ (100 nm thick). The step coverage revealed two deposition regimes: a surface reaction controlled regime for cavities aspect ratio lower than 2 and a diffusion-controlled regime for higher aspect ratios. The ZrO₂ films present mostly a cubic/tetragonal structure. The permittivity extracted from the measurement is 26.4. These results are discussed with static dielectric responses calculated in literature.     

Ultrathin HfO2 gate dielectrics on partially strain compensated SiGeC/Si heterostructure

Ultrathin HfO₂ gate dielectrics have been deposited on strain-compensated Si_0.69Ge_0.3C_0.01 layers by rf magnetron sputtering. X-ray diffraction spectra show the films to be polycrystalline having both monoclinic and tetragonal phases. The formation of an interfacial layer has been observed by high-resolution transmission electron microscopy. Secondary ion mass spectroscopy and Auger electron spectroscopy analyses show the formation of an amorphous Hf-silicate interfacial layer between the deposited oxide and SiGeC films. The average concentration of Ge at the interfacial layer is found to be 2–3 at%. The leakage current density of HfO₂ gate dielectrics is found to be several orders of magnitude lower than that reported for thermal SiO₂ with the same equivalent thickness.     

Electrical properties of high permittivity ZrO2 gate dielectrics on strained-Si

Deposition and electrical properties of high dielectric constant (high-k) ultrathin ZrO₂ films on tensilely strained silicon (strained-Si) substrate are reported. ZrO₂ thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage (C–V), current–voltage (I–V), and conductance–voltage (G–V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectrics. Compatibility of ZrO₂ as a gate dielectric on strained-Si is shown.     

Electrical characterization of high-pressure reactive sputtered ScOx films on silicon

Al/ScO_x/SiN_x/n-Si and Al/ScO_x/SiO_x/n-Si metal-insulator-semiconductor capacitors have been electrically characterized. Scandium oxide was grown by high-pressure sputtering on different substrates to study the dielectric/insulator interface quality. The substrates were silicon nitride and native silicon oxide. The use of a silicon nitride interfacial layer between the silicon substrate and the scandium oxide layer improves interface quality, as interfacial state density and defect density inside the insulator are decreased.     

Atomic Vapor Depositions of Ti-Ta-O thin films for Metal-Insulator-Metal applications

Atomic Vapor Deposition technique was applied for the depositions of Ti-Ta-O oxide films for Metal-Insulator-Metal capacitors used in back-end of line for Radio Frequency applications. Composition, crystallinity, thermal stability and electrical properties were studied. Ti-Ta-O films, with the ratio of Ta/Ti ~ 1.5, deposited at 400 °C on TiN electrodes, were amorphous and possessed a dielectric constant of 50 with low voltage linearity coefficients and leakage currents densities as low as 10^− 7 A/cm² at 1 V. The films, deposited on Si wafers, were amorphous up to the annealing temperature of 700 °C and crystallized in orthorhombic Ta₂O₅ phase at higher temperatures.     

Enhanced leakage current behavior of Sr2Ta2O7−x/SrTiO3 bilayer dielectrics for metal-insulator-metal capacitors

Metal-Insulator-Metal (MIM) capacitors are one of the most essential components of radio frequency devices and analog/mixed-signal integrated circuits. In order to obtain high capacitance densities in MIM devices, high-k materials have been considered to be promising candidates to replace the traditional insulators. The challenging point is that the dielectric material must demonstrate high capacitance density values with low leakage current densities.In this work, SrTiO₃ based MIM capacitors have been investigated and the electrical performance of the devices have been optimized by using bilayered systems of Sr₂Ta₂O_7−x/SrTiO₃ with different thicknesses of Sr₂Ta₂O_7−x. Sputtering X-Ray photoelectron spectroscopy (XPS) measurements have been applied to investigate the interfaces between the thin film constituents of the MIM stacks. The optimized bilayered system provides a leakage current density of 8∗10^− 8 A/cm² at 2 V (bottom electrode injection) and a high capacitance density of 13 fF/μm².     

Millisecond flash-lamp annealing of LaLuO3

Metal-oxide-semiconductor capacitors containing the alternative high-k dielectric LaLuO₃ were treated by flash lamp annealing (FLA). Capacitance-voltage (C-V) and current-voltage (J-V) characteristics reveal an increase in the capacitance for the flashed samples while the very low leakage current of the LaLuO₃ is retained. Microstructural investigations confirm the thermal stability of the film even after FLA at 1200 °C, 20 ms.