Towards barrier height modulation in HfO2/TiN by oxygen scavenging - Dielectric defects or metal induced gap states?

The band alignment between a dielectric and a metal gate is crucial as it controls the MOSFET threshold voltage as well as the leakage in metal-insulator-metal (MIM) structure. In the ideal Schottky-Mott model the barrier height should be controlled only by the workfunction and the electron affinity of the materials considered. However, this seems the case only for few insulating materials other than SiO₂ (i.e., Fermi level pinning).The most popular explanation invokes metal-induced gap states (MIGS), where electron states from the bulk of a metal tails into the insulator. The MIGS hypothesis explains a rather large series of experimental results and, importantly, predicts that the MI barrier height will mostly be controlled by the energy distribution of electron states in the bulk of the contacting metal and dielectric. In this paper, we analyze the band alignment of contacting metal (TiN) and dielectric (HfO₂) by using internal photoemission. It will be shown that defects in the dielectric rather than MIGS control the barrier height.     

堆叠栅介质MOS器件栅极漏电流的计算模型

采用顺序隧穿理论和传输哈密顿方法并考虑沟道表面量子化效应,建立了高介电常数堆叠栅介质MOS器件栅极漏电流的顺序隧穿模型。利用该模型数值,研究了Si3N4/SiO2、Al2O3/SiO2、HfO2/SiO2和La2O3/SiO2四种堆叠栅介质结构MOS器件的栅极漏电流随栅极电压和等效氧化层厚度变化的关系。依据计算结果,讨论了堆叠栅介质MOS器件按比例缩小的前景。     

Investigation of the analysis parameters and background subtraction for high-k materials with atom probe tomography

In this paper we present depth profiles of a high-k layer consisting of HfO₂ with an embedded sub-nm thick ZrO₂ layer obtained with atom probe tomography (APT). In order to determine suitable measurement parameters for reliable, reproducible, and quantitative analysis, we have investigated the influence of the laser energy and the specimen temperature on the resulting elemental composition. In addition we devise a procedure for local background subtraction both for the composition and the depth scale that is crucial for gaining reproducible results. We find that the composition of the high-k material remains unaffected even for extreme laser energies and base temperatures, while higher laser energies lead to an accumulation of silicon at the upper interface of the high-k layer. Furthermore we show that APT is capable of providing sub-nm depth resolution for high-k materials with high reproducibility, good compositional accuracy, and high measurement yield.     

Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack

A comparison between pMOS and nMOS short channel transistors with high-k dielectric subjected to channel hot-carrier (CHC) stress is presented. Smaller CHC degradation is observed in pMOS devices. At high temperature, the CHC degradation increases for pMOS and nMOS. The temperature dependence of the CHC degradation has been explained, for both transistor types, by considering a larger influence of a bias temperature instability (BTI)-related component of the total CHC induced degradation.     

Electrical properties of vacuum annealed La2O3 thin films grown by E-beam evaporation

In this article, the conduction mechanisms of metal-oxide-semiconductor with vacuum annealed Lanthana (La₂O₃) oxide film are investigated. Lanthana films with thicknesses of 3.5, 4.7, and 11 nm were deposited by E-beam evaporation on n-Si (100), and annealed at various temperatures (300-500 °C) in ultra-high vacuum (10⁻¹⁰-10⁻⁹ Torr) for 90 min. From the measurement of spectroscopic ellipsometry, it is found that film thickness is increased with annealing temperature, which would be cause of flat-band voltage shift (ΔV_FB) due to the growth of interfacial layer. From the capacitance measurement, it is found that ΔV_FB of the film is reduced by post-deposition anneal (PDA) compared to that of as-deposited film, but increase again at high temperature annealing, especially in the case of thin film (3.5 nm). From the applied voltage and temperature dependence of the leakage current of the film, with different gate electrode materials (Ag, Al, and Pt), it is shown that the leakage currents are associated with ohmic and Poole-Frenkel (P-F) conductions when flat-band voltage (V_FB) is less than zero, and ohmic and Space-Charge-Limited Current (SCLC) conductions when V_FB is greater than zero. The dielectric constants obtained from P-F conduction for Al gate electrode case is found to be 11.6, which is consistent with the C-V result 11.9. Barrier height of trap potential well is found to be 0.24 eV from P-F conduction. Based on SCLC theory, leakage currents of 3.5 and 11 nm films with different PDA temperatures are explained in terms of oxide trap density.     

Photoconductivity of Hf-based binary metal oxides

In order to explore the possibility of bandgap engineering in binary oxide insulators we studied photoconductivity of nanometer-thin Hf oxide layers containing different fractions of cations of another sort (Si, Al, Sr, or Ce) deposited on (1 0 0)Si. The smallest bandgaps of the Hf:Al and Hf:Ce oxides are close to the values found in elemental Al₂O₃ (6-6.2 eV) and HfO₂ (5.6 eV), respectively, and show little sensitivity to the concentration of Al or Ce. This result suggests that the oxide sub-network with the largest bandgap preserves its gap energy, while development of a narrower gap is prevented, likely, by dilution of the second cation sub-network. In Hf:Si oxide samples photoconductivity thresholds of 5.6-5.9 eV, corresponding to the bandgap of HfO₂, were observed for all studied Si concentrations, suggesting phaseseparation to occur during deposition. Photoconductivity of SrHfO₃ exhibits two thresholds, at 4.4 and 5.7 eV, which are close to the bandgaps of elemental SrO₂ and HfO₂, respectively. These gap values indicate the phase separation also to occur in this binary oxide. Through this work photoconductivity is demonstrated to be a feasible method to trace phase separation in binary oxides, even in nanometer-thin layers.     

Aqueous solution-processed,self-flattening AlOx:Y dielectrics for fully-transparent thin-film transistors

Dielectrics fabrication on rough substrates, always leading to microstructural defects and detrimental dielectric properties eventually, is a great challenge for academic endeavors in this field. We report here on self-flattening AlO_x:Y dielectric thin films processed by a facile aqueous solution method. The obtained AlO_x:Y dielectrics are dense, large-area uniform, and amenable to accurate control of film thickness by repeating the deposition cycles. In particular, an atomically smooth surface with a RMS of 0.10 nm was realized for the AlO_x:Y film with a thickness of 14.5 nm on Si wafer, yielding a low leakage current density of 7.9 × 10^-8 A cm^-2@2 MV/cm, a dielectric constant of 8.8 @100 Hz, and an attenuated dielectric dispersion property. The interactions between pre-baked YO_x underlayer and later-dropped AlO_x precursor were comprehensively investigated, in order to understand the film growth mechanism and the origin of self-flattening effect. Fortunately, this self-flattening effect is also applicable to other substrates. A RMS of 0.81 nm was achieved on ITO glasses, and the height distribution profile of the film surface was found to follow symmetric Gaussian distribution. This preparation routine was also examined by device verification in the fully-transparent thin-film transistors. The combination of ease of preparation and attractive physical properties would provide a green-route solution platform for dielectric synthesis, for interface engineering, and for well-performed devices on rough substrates.     

Growth characteristics and electrical properties of La2O3 gate oxides grown by thermal and plasma-enhanced atomic layer deposition

We comparatively investigated thermal and plasma-enhanced atomic layer deposition (T-ALD and PE-ALD, respectively) of lanthanium oxide (La₂O₃) films using tris(isopropyl-cyclopentadienyl)lanthanum [La(iPrCp)₃] as a La precursor. H₂O and O₂ plasma were used as reactants for T-ALD and PE-ALD La₂O₃, respectively. Both of the processes exhibited ALD mode growth with good self-saturation behavior and produced pure La₂O₃ films. However, PE-ALD La₂O₃ showed higher growth rate and dielectric constant value than those of T-ALD La₂O₃. In addition, lower leakage current density and interface state density were observed for PE-ALD La₂O₃, compared to those of the T-ALD La₂O₃. These experimental results indicate that the PE-ALD La₂O₃ process using La(iPrCp)₃ precursor can be one of the viable options applicable into future microelectronic industry.     

Electrical properties of Ge metal-oxide-semiconductor capacitors with La2O3 gate dielectric annealed in different ambient

Ge metal-oxide-semiconductor capacitors with La₂O₃ as gate dielectric are fabricated by e-beam evaporation of La₂O₃ followed by post-deposition annealing in different gases (NH₃, N₂, NO, N₂O and O₂). Experimental results indicate that the NH₃, NO, N₂O and O₂ anneals give higher interface-state and oxide-charge densities, and thus larger gate leakage current, with the highest for the O₂ anneal due to the growth of an unstable GeO_x interlayer. On the other hand, the NH₃ annealing improves the k value of the dielectric, while the annealings in O₂-containing ambients (NO, N₂O and O₂) lead to the formation of a low-k GeO_x interlayer, thus decreasing the equivalent k value. Compared with the above four samples, the sample annealed in N₂ exhibits not only larger k value (18.3) and smaller capacitance equivalent thickness (2.14 nm), but also lower leakage current density (~ 10⁻³ Acm^− 2 at V_g = 1 V) and smaller interface-state density (4.5 × 10¹¹ eV^− 1 cm^− 2).     

Profiling of traps in SiO2/Al2O3 gate stack by the charge pumping technique

In this paper, we present our results on the distribution and generation of traps in a SiO₂/Al₂O₃ transistor. The investigation has been carried out by using charge pumping measurements, both variable voltage and frequency techniques, and constant voltage stress.By increasing the amplitude of the gate pulse we observe an increase of the charge recombined per cycle closely related to the contribution of shallow traps near the SiO₂/Al₂O₃ interface. By reducing the pulse frequency we measure an increase in the charge pumping current due to traps located deeper in the Al₂O₃. By combining charge pumping and constant voltage stress measurements, we found that the traps are mostly generated near the Si/SiO₂ interface.