一种高精度的带隙基准电压源及电流源

设计了一种采用0．25μm CMOS工艺的高精度带隙基准电压源，该电路结构新颖，性能优异，其温度系数可达5ppm／℃，电源抑制比可达到62dB。在此基础上设计了一种基准电流源，其温度系数可达6ppm／℃，输出电流变化率仅为0．03％／V。     

智能CMOS集成温度传感器设计

基于标准0．18μm CMOS工艺和低功耗设计方法设计了集成温度传感器所需的3个重要电流产生电路，即与温度成正比的电流，与温度成反比的电流和稳定的、不随温度及电源电压变化的电流产生电路。采用低功耗设计方法解决了自然效应对温度传感器的影响。采用TSMC所提供的BSIM3V3模型进行仿真，电路在-40～120℃具有高线性度、高稳定度。同时电路具有低压、低功耗的优点，并且有良好的移植性，可使用于更多更广泛的吻合。     

A low-power cryogenic analog to digital converter in standard CMOS technology

This paper presents a cryogenic successive approximation register (SAR) based analog to digital converter (ADC) in standard 0.35 μm complementary metal oxide semiconductor (CMOS) technology that functions from 300 K (room temperature) down to 20 K. It has been designed to operate in low temperature mid- and far-infrared imaging systems. In order to ensure the circuit performance at the extreme temperatures, a dedicated integral-based comparator architecture is employed. SPICE models have been developed for circuit simulation at 20 K. At 20 K, the experimental results exhibit that the ADC achieves 1.6 LSB maximum differential nonlinearity (DNL), 1.7 LSB maximum integral nonlinearity (INL), and 10.4 effective number of bits (ENOB) at 100 kS/s sampling rate with a current consumption of 75 μA from a 3.3 V supply.     

Design of 60GHz RF Transceiver in CMOS:Challenges and Recent Advances

With more than 40 years Moore scaling, the speed of CMOS transistors is around 100 GHz. Such fact makes it possible to realize mm-wave circuits in CMOS. However, with the target of achieving broadband and power-efficient operation, 60 GHz CMOS RF transceiver faces severe challenges. After reviewing the technology issues, regarding the 60 GHz applications, this paper discusses design challenges both from the system and the building block levels, and also presents some simulated or measured circuits results.     

Substrate noise isolation improvement in a single-well standard CMOS process

This work describes a fully CMOS compatible methodology, which makes available a pseudo deep n-well in single-well standard CMOS process. The proposed method is based on mask manipulation to accommodate the field implant p-type region into the n-well, and does not require any additional masks or modification in the CMOS process flow. According to the experimental results, the floating NMOS made available by the methodology shows a reduction in the threshold voltage, which implies a slight improvement in its performance, when compared with its standard NMOS counterpart. It was also experimentally demonstrated up to 3 GHz, that the guard-ring field implant/pseudo deep n-well proposed structure improves substrate noise isolation when compared to the classical p+ guard-ring, with a maximum improvement above 20 dB for low frequencies and a minimum of 4 dB at 3 GHz.     

循环流化床锅炉风机变频节能改造

本文介绍了高压变频器在寿光金太阳热电厂75t/h循环流化床锅炉的应用情况,应用实例表明,使用高压变频系统,改善了设备的运行工况,用户节能效果明显。     

A wireless multi-channel implantable neural recording microsystem based on optimized analog TDM-FDM combination

Crosstalk noise (CT) is a limiting factor to increase the number of channels in analog Time-Division-Multiplexing (TDM)-based Wireless Neural Recording microsystems (WNRs). This paper proposes a novel approach to mitigate and decrease the effect of the CT by combining TDM with Frequency-Division-Multiplexing (FDM). In particular, we evaluate some possible configurations of the TDM-FDM combination and present a system that has less CT than other configurations. A 12-channel WNR based on the proposed system is designed in both system and circuit-level. In this system, channels are first divided into three 4-channel groups and after multiplexing in time domain, they are combined together with FDM method. While the group containing the marker pulse is located in the base-band, the second and third group are shifted to the frequency domain by employing quadrature modulation. The circuit-level of the system is designed and simulated by using 0.18 μm CMOS technology. The designed circuit consumes a power of 1.4 mW at a supply voltage of 1.8 V. The performance of the proposed system is also compared with simple TDM-based WNR. Simulations shows that in the proposed system the CT is considerably decreased.     

Memristor emulator with tunable characteristic and its experimental results

In this study, operational transconductance amplifier (OTA) based simple and practical TiO₂ memristor emulator is presented. The proposed memristor emulator employs a multi-outputs OTA, an analog multiplier and a resistor and a capacitor. The parameters of the proposed memristor emulator can be tuned electronically by changing the biasing current of the OTA. Change of the transconductance gain of the OTA provides an advantage: “externally controllable memristor”. Non-volatile resistive switching characteristics and an application of this proposed memristor are given. Also, the memristor emulator is implemented using the commonly available OPA860. The effectiveness of the proposed memristor emulator is verified by the experimental results, which show good agreement with the theoretical and simulation results.     

一种用于电流型电化学传感器的CMOS模拟前端芯片

本文提出了一种用于电流型电化学传感器的CMOS模拟前端芯片,芯片具有高度可编程性,其内部集成了可通过I2C接口总线与外部控制芯片通信的可配置数字模块电路。结合incremental型sigma-delta模数转换器与数字域相关双采样技术,提出并实现了一种新的两次采样的系统架构。该芯片基于华虹宏力0.18μm标准CMOS工艺流片,消耗芯片面积为1.3 mm × 1.9 mm,测试结果表明：该芯片16位数字输出具有高精度,高线性度特性,可检测溶液中磷酸根离子浓度的精度为0.01 mg/L。     

MCML结构高速数模转换器的设计

本文基于MCML结构,采用TSMC 0．18μm 1P6M CMOS标准工艺设计方法,通过模拟仿真试验,设计出了一个8位分段式全温度计编码的高速数模转换器,该电路在采样频率为1 GHZ,输入正弦波频率为122 MHz时,SFDR达到了58．35 dB,在采样频率为2 GHZ,输入正弦波频率为244 MHz时,SFDR达到了50．21 dB。