High performance InP JFETs grown by MOCVD using tertiarybutylphosphine

Indium phosphide channel junction field effect transistors were fabricated by metalorganic chemical vapor deposition using tertiarybulylphosphine (TBP) as the alternative source for phosphine. At growth temperatures of 600°C, InP with specular surface morphology and mobilities as high as 61000 cm₂/V s at 77Khas been achieved using trimethylindium and TBP. To improve device isolation, pinch-off characteristics, and output transconductance, we employ a high resistivity (1 × 10⁸ Ω-cm) semi-insulating InP buffer layer using ferrocene as the Fe-dopant. Devices with gate lengths of 1 urn exhibit very high extrinsic transconductance of 130 mS/mm, gate-drain breakdown voltage exceeding 20 V, maximum current density of >450 mA/mm with record high f_T and f_max of 15 GHz and 35 GHz, respectively. These results indicate: that InP JFETs are promising electronic devices for microwave power amplification, and that TBP is capable of device quality materials.     

SiC JFET功率特性的仿真与优化

建立了常关型SiC结型场效应晶体管(JFET)功率特性的数值模型,研究了不同的结构和材料参数对器件功率特性的影响。仿真结果显示,沟道层、漂移层等各层的厚度及掺杂浓度对器件的开态电阻和击穿电压都有明显的影响;采用电流增强层可以明显提高器件的功率特性。研究结果表明,对SiC JFET的结构参数进行优化,可以有效提高器件的优值(FOM)。     

SiC肖特基栅JFET功率特性的研究

提出了一种新型结构的SiC结型场效应晶体管,采用肖特基接触替代P+型栅区,以降低SiC JFET的工艺复杂度,并提高器件的功率特性。建立了器件的数值模型,对不同材料和结构参数下的功率特性进行了仿真。结果表明,与PN结栅相比,肖特基栅结构可以有效降低SiC JFET的开态电阻;与常规结构的双极模式SiC JFET相比,在SiC肖特基栅JFET的栅极正偏注入载流子,同样可以有效降低器件的开态电阻,折中器件的正反向特性,但不会延长开关时间。     

不同碳化硅器件的直接比较

本文介绍了意法半导体公司(STMicroelectronics)首次提出的1200V/20A的SiC MOSFET,并与1200V常闭型SiC JFET(结型场效应晶体管)和1200V SiC BJT(双极结型晶体管)作对比。全面比较了3种开关器件工作在T=25℃、电流变化范围(1A~7A)的动态特性,并在T=125℃、ID=7A条件下做了快速评估。尽管SiC MOSFET的比通态电阻(Ron*A)很高,但与另外两种器件相比仍被认为是最有前景的开关器件:SiC MOSFET的总动态损耗远远低于SiC BJT和常闭型SiC JFET,且驱动方案非常简单。因此在高频、高效功率转换领域中,SiC MOSFET是最好的选择。     

Fabrication of a Thermally Isolated and Pre-Amplified Transistor Module with Polyimide Micro-Wires for Cryogenic Detectors

We report a pre-amplifying junction field effect transistor (JFET) module on a chip for cryogenic applications such as bolometer and X-ray microcalorimeter. In order to maintain the optimum performance of the JFETs at 130 K, the module has built-in aluminum micro-heaters while the JFETs are thermally isolated from a heat sink. The thermal isolation is achieved by suspending a micromachined silicon support platform (6 μm thick) with polyimide wires. A layer of aluminum electrodes is patterned on top of the polyimide wires for electrical contacts and on top of the silicon platform for the heaters. This process involves reactive-ion-etching (RIE) of silicon and polyimide, patterning of aluminum electrodes over the polyimide, back side deep-reactive-ion-etching (DRIE) of silicon, and releasing of the modules. In this paper, we describe a micromachining process of the JFET modules on silicon-on-insulator (SOI) wafers.      

An analogue model of the memristor

The paper presents a working electrical scheme modeling the memristor. The scheme allows experimenting with the model under various testing signals. The user can use it to verify the theoretical presumptions about the memristor properties. Examples of several typical measurements are shown. Copyright © 2010 John Wiley & Sons, Ltd.     

新型固体LBCAST JFET图像传感器

尼康公司的D2H单反数字相机中使用了一种新型的固体图像传感器LBCASTJFET。该器件在读数方式、内部结构等方面有了较大改进,与CCD、CMOS图像传感器比较具有瞬时启动、高灵敏度、高分辨率、低能耗、成品率高和低噪声等特色。     

Comparison of Mg and Zn gate implants for GaAs n-channel junction field effect transistors

Zinc and magnesium implants into GaAs were profiled with secondary ion mass spectroscopy and etching capacitance-voltage to measure the as-implanted and annealed profiles for the eventual formation of shallow p⁺/n junction gates for junction field effect transistors (JFETs). The larger mass of the zinc ions results in shorter projected range with significantly less tailing than magnesium implants. High dose, shallow zinc implants annealed under tungsten gate metal showed good activation with negligible diffusion. The improved profile of the zinc implant, as compared to a similar magnesium implant, allowed a tighter JFET design with increased performance. Zn gated n-channel enhancement mode GaAs JFETs with 0.9 μm gate lengths showed transconductances up to 200 mS/ mm with a f_t of 18 GHZ and a f_max of 37 GHz. The performance of these self-aligned fully implanted JFETs compare favorably with comparably sized implanted MESFETs.     

运算放大器中JFET对管的制作技术及其发展前景

JFET与双极器件相结合,可以获得高速/宽带/高输入阻抗的运算放大器。但由于工艺水平的限制,Bi-JFET单片兼容工艺中的场效应器件的特性并不很理想,影响了电路的性能。目前的高性能场效应运放,基本上是采用高性能JFET对管与纵向p-n-p、n-p-n混合组装而成。本文分析了场效应运放中场效应器件制作技术的发展,提出了两种新的单片高性能JF-ET对管与高性能纵向p-n-p、n-p-n兼容工艺,以期能结合自动稳零技术,制造出单片高速、宽带、高输入阻抗、低失调、高精度运放。     

2D array of cold-electron nanobolometers with double polarised cross-dipole antennas

ABSTRACT: A novel concept of the two-dimensional (2D) array of cold-electron nanobolometers (CEB) with double polarised cross-dipole antennas is proposed for ultrasensitive multimode measurements. This concept provides a unique opportunity to simultaneously measure both components of an RF signal and to avoid complicated combinations of two schemes for each polarisation. The optimal concept of the CEB includes a superconductor-insulator-normal tunnel junction and an SN Andreev contact, which provides better performance. This concept allows for better matching with the junction gate field-effect transistor (JFET) readout, suppresses charging noise related to the Coulomb blockade due to the small area of tunnel junctions and decreases the volume of a normal absorber for further improvement of the noise performance. The reliability of a 2D array is considerably increased due to the parallel and series connections of many CEBs. Estimations of the CEB noise with JFET readout give an opportunity to realise a noise equivalent power (NEP) that is less than photon noise, specifically, NEP = 4*10^-19 W/Hz^1/2 at 7 THz for an optical power load of 0.02 fW.