运算放大器中JFET对管的制作技术及其发展前景

JFET与双极器件相结合,可以获得高速/宽带/高输入阻抗的运算放大器。但由于工艺水平的限制,Bi-JFET单片兼容工艺中的场效应器件的特性并不很理想,影响了电路的性能。目前的高性能场效应运放,基本上是采用高性能JFET对管与纵向p-n-p、n-p-n混合组装而成。本文分析了场效应运放中场效应器件制作技术的发展,提出了两种新的单片高性能JF-ET对管与高性能纵向p-n-p、n-p-n兼容工艺,以期能结合自动稳零技术,制造出单片高速、宽带、高输入阻抗、低失调、高精度运放。     

2D array of cold-electron nanobolometers with double polarised cross-dipole antennas

ABSTRACT: A novel concept of the two-dimensional (2D) array of cold-electron nanobolometers (CEB) with double polarised cross-dipole antennas is proposed for ultrasensitive multimode measurements. This concept provides a unique opportunity to simultaneously measure both components of an RF signal and to avoid complicated combinations of two schemes for each polarisation. The optimal concept of the CEB includes a superconductor-insulator-normal tunnel junction and an SN Andreev contact, which provides better performance. This concept allows for better matching with the junction gate field-effect transistor (JFET) readout, suppresses charging noise related to the Coulomb blockade due to the small area of tunnel junctions and decreases the volume of a normal absorber for further improvement of the noise performance. The reliability of a 2D array is considerably increased due to the parallel and series connections of many CEBs. Estimations of the CEB noise with JFET readout give an opportunity to realise a noise equivalent power (NEP) that is less than photon noise, specifically, NEP = 4*10^-19 W/Hz^1/2 at 7 THz for an optical power load of 0.02 fW.     

Proposal of preliminary device model and scaling scheme of cross-current tetrode SOI MOSFET aiming at low-energy circuit applications

This paper describes a preliminary attempt with a semi-analytical model and a scaling scheme of the cross-current tetrode (XCT) silicon-on-insulator (SOI) MOSFET aiming at low energy-dissipation circuit applications. The channel-current model for XCT MOSFET is separated into an intrinsic MOSFET part and a parasitic junction-gate field-effect transistor (JFET) part. Models for MOSFET and JFET are proposed by taking the potential coupling between MOSFET and JFET. The later part of the paper introduces experiments on the original SOI nMOSFET and XCT nMOSFET. This paper stresses the fundamental operations and features of the XCT device structure. Calculation results of I-V characteristics from the semi-analytical model are compared with the measurement values. It is shown that the proposed model reproduces the measured values successfully. In addition, design guidelines for XCT devices and scaling issues are discussed from the viewpoint of performance control aiming at low energy-dissipation circuit applications. Finally, preliminary circuit simulation results of XCT CMOS devices are revealed to demonstrate the definite low-energy performance.     

面向低压高频开关应用的功率JFET的功耗

提出了一种埋氧化物槽栅双极模式功率JFET(BTB-JFET),其面向低压高频开关应用。首次通过仿真对BTB-JFET、常规的槽栅双极模式JFET(TB-JFET)和槽栅MOSFET(T-MOSFET)等20V级的功率开关器件在高频应用时的功率损耗进行了比较。仿真中借鉴现有的高性能T-MOSFET的结构尺寸,并采用了感性负载电路对器件进行静态以及混合模式的电特性仿真,结果表明,常开型BTB-JFET与TB-JFET相比,零偏压时栅漏电容CGD减小25%;当工作频率为1MHz和2MHz时常开型TB-JFET与T-MOSFET相比总功耗分别降低了14%和19%,而常开型BTB-JFET较TB-JFET的总功耗又进一步降低了6%。仿真结果还表明,在不同工作频率下,常闭型JFET的性能都不如T-MOSFET。样管初步测试结果证明,常开型BTB-JFET与TB-JFET相比,零偏压时栅漏电容CGD减小45%,与仿真结果相一致。     

NJFET器件饱和电流影响因子及工艺优化研究

针对N沟道结型场效应晶体管(NJFET)在工艺制造过程中极易出现饱和电流一致性差的问题,从一次氧化、栅注入和栅推结等方面对饱和电流工艺影响因子开展了实验研究,并提出了工艺优化和控制方法,使器件饱和电流参数得到有效控制,一致性由6.90%改善至0.38%,圆片对档率由85%提升到96%以上,提升了器件产品质量,降低了成本。     

The determination and importance of internal capacitances of transistors in the frequency band of commercial FM broadcasting

Using a single-capacitor Colpitts oscillator a method has been proposed for determination of internal capacitances of bipolar junction transistors (BJTs) and junction field effect transistors (JFETs) in the frequency band of commercial frequency modulation (FM) broadcasting. Variation of these capacitances with the operating bias point and the operating frequency of the active device has been considered. Practical implementation of this method does not require any unconventional measuring system. The changing behavior of the base-emitter capacitance of BJTs versus operating bias current has been utilized for designing a simple high-frequency amplitude-modulating (AM) system. This efficiently designed AM signal generator does not have any transformer and is an example showing the importance of internal capacitances of active devices.     

基于级联常通型SiC JFET的快速中压直流固态断路器设计及实验验证

固态断路器(solid state circuit breaker, SSCB)是直流配电网中实现快速、无弧隔离直流故障的关键保护装置。首先提出了一种基于级联常通型碳化硅(silicon carbide, SiC)结型场效应晶体管(junction field effect transistor, JFET)的新型中压直流SSCB拓扑,直流故障发生时利用金属氧化物压敏电阻(metal oxide varistor, MOV)向SSCB主开关级联常通型SiC JFET器件的栅源极提供驱动电压,可快速实现直流故障保护。其次详细分析了SSCB关断和开通过程的运行特性,并提出了SSCB驱动电路关键参数设计方法。最后研制了基于3个级联常通型SiC JFET器件的1.5 kV/63 A中压SSCB样机,通过短路故障、故障恢复实验验证了设计方法的有效性。结果表明该SSCB关断250 A短路电流的响应时间约为20 s,故障恢复导通响应时间约为12 s,为中压直流SSCB的拓扑优化设计和级联常通型SiC JFET器件的动静态电压均衡性能提升提供了支撑。     

智能型高压SENSFET器件的设计分析和实现

基于JFET原理,采用Double RESURF技术,对SENSFET的降场层注入剂量、始点位置和长度以及Nwell注入剂量等进行优化设计,得到了耐压730V、JFET线性区电阻为7.2×105Ω·μm的智能高压SENSFET器件.流片结果表明,器件宽度为75μm情况下,SENSFET的击穿电压为700V,线性区电阻为10kΩ.设计分析和实验结果吻合得很好.借助该SENSFET器件可以很好地实现智能功率集成电路中高压器件的信号检测和电路的自供电功能.     

Channel electron mobility in 4H–SiC lateral junction field effect transistors

Interface defects have limited 4H–SiC MOS-based FET channel mobility to less than 40–50 cm²/V s after more than 10 years of improvement. Junction-based FET, on the other hand, presents an excellent opportunity. This paper will report the realization of a record high channel mobility of 398 cm²/V s for 4H–SiC lateral junction FET. The fabrication and characterization as well as computer modeling results will be presented. The application of this very high channel mobility will also be discussed.     

CPU电源电路用沟槽栅MOSFET与e-JFET开关管的功耗对比

本文主要针对低压功率开关管的功耗进行了理论分析，并在此基础上分别对两种典型结构的沟槽栅MOSFET和e—JFET在不同工作频率下的功耗分布和总功耗进行了定量的仿真计算和对比。通过研究发现，在一定工作条件下，常闭型e-JFET比目前常用的沟槽栅型MOSFET仅开关功耗就降低约24％，总功耗则降低约30％。将其运用于CPU电源电路中的开关功率管的制造，在高频领域有着极好的应用前景。