Carbon nanotube integrated 3-dimensional carbon microelectrode array by modified SU-8 photoresist photolithography and pyrolysis

An integration strategy is devised for a reliable and scalable assembly of carbon nanotubes in photoresist-derived glassy-like carbon microelectrodes. The approach involves UV photolithography process with carbon nanotube monodispersed photoresist followed by high temperature pyrolysis process, and is versatile in yielding various 3-dimensional micro-nano integrated carbon microelectrode arrays. The morphology of the micro-nano integrated structures is characterized. The integrated microelectrodes demonstrate better electrical performance than the blank microelectrodes, showing potential applications in high-sensitive chemical and biological detection systems. The developed method represents a low-cost and facile way to mass production of carbon nanotube-integrated carbon microelectrode array.     

高亮度LED步进投影光刻机及其量产应用

图形化蓝宝石衬底(PSS)工艺在改善GaN晶体外延生长质量以及提升LED器件发光提取效率方面作用显著,并被LED行业大量采用。针对高亮度LED量产线大量采用二手投影光刻机制备PSS衬底所面临的焦深不足、垂向控制容易离焦,以及运动台拼接精度不足等问题导致的PSS良率仅有70%~80%的现象,有针对性地在新研制的高亮度LED光刻机中采用最佳线宽/焦深选择技术、无缝拼接技术、Mapping垂向控制技术,使PSS的制造良率达到95%以上,极大地降低了PSS制造返工成本。同时,针对芯片细电极曝光需求,采用精密机器视觉对准技术,实现了芯片电极层1μm线宽下200 nm套刻精度。     

高精度机器视觉对准测量系统设计

设计了用于半导体先进封装光刻设备中的高精度机器视觉对准测量系统,明确了机器视觉对准测量系统工作原理、设计指标及系统设计中需要考虑的关键技术点,同时给出了机器视觉对准测量系统关键零部件的设计,并给出了对准测量系统最终在整机上测得的性能数据。测试结果表明,所设计的机器视觉对准测量系统完全可以满足集成电路先进封装工艺需求。     

晶片传输系统中切边探测和预对准技术

介绍投影光刻机设备的晶片传输系统中切边探测和晶片预对准技术。     

Laser‐Induced Direct Lithography for Patterning of Carbon with sp3 and sp2 Hybridization

A new method of laser‐induced lithography for direct writing of carbon on a glass surface is described, in which deposition occurs from a transparent precursor solution. At the glass–solution interface where the laser spot is focused, a micro‐explosion process takes place, leading to the deposition of pure carbon on the glass surface. Transmission electron microscopy (TEM) analysis shows two distinct co‐existing phases. The dominant one shows a mottled morphology with diffraction typical of cubic (sp³) diamond. The other region shows an ordered array of graphene sheets with diffraction pattern typical of sp²‐bonded carbon. The sp³ crystallites range in size from 9 to 30 Å and are scattered randomly throughout the sample. A UV Raman spectrum shows a broad band at the location of the expected diamond peak, together with a peak corresponding to the graphite region. We conclude that the patterned carbon is composed of a mixture of nanocrystalline sp³ and sp² carbon forms.     

Dose control circuit for digital electrostatic electron-beam array lithography

This paper demonstrates a technique for controlling the electron emission of an array of field emitting vertically aligned carbon nanofibers (VACNFs). An array of carbon nanofibers (CNF) is to be used as the source of electron beams for lithography purposes. This tool is intended to replace the mask in the conventional photolithography process by controlling their charge emission using the “Dose Control Circuitry” (DCC). The large variation in the charge emitted between CNFs grown in identical conditions forced the controller design to be based on fixed dose rather than on fixed time. Compact digital control logic has been designed for controlling the operation of DCC. This system has been implemented in a 0.5 μm CMOS process. Chandra Sekhar A. Durisety received his B.E. (Hons.) Instrumentation from Birla Institute of Technology and Sciences, Pilani, India in 1997 and his M.S in Electrical Engineering from University of Tennessee, Knoxville in 2002. Since 2003, he has been working towards his Ph.D degree also in Electrical Engineering at Integrated Circuits and Systems Lab (ICASL), University of Tennessee, Knoxville. He joined Wipro Infotech Ltd, Global R & D, Bangalore, India in 1997, where he designed FPGA based IPs for network routers. Since 1999, he was involved in the PCI bridge implementation at CMOS chips Inc, Santa Clara, CA, and the test bench development for Sony’s MP3 player, while at Toshiba America Electronic Components Inc., San Jose, CA. His research interests include multi-stage amplifiers, data converters, circuits in SOI and Floating Gate Devices. Rajagopal Vijayaraghavan received the B.E degree in electronics and communication engineering from Madras University in 1998 and the M.S degree in electrical engineering from the University of Texas, Dallas in 2001.He is currently working towards the Ph.D degree in electrical engineering at the University of Tennessee. His research interest is in the area of CMOS Analog and RF IC design. His current research focuses on LNAs and VCOs using SOI based MESFET devices. Lakshmipriya Seshan was born in Trivandrum, India on April 30, 1979. She received her B.tech in Electronincs & Communication Engg from Kerala University, India in June 2000 and M.S in Electrical Engg from University of Tennessee in 2004. In 2004, she joined Intel Corporation as an Analog Engineer, where she is engaged in the design of low power, high speed analog circuits for various I/O interface topologies. Syed K. Islam received his B.Sc. in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (BUET) and M.S. and Ph.D. in Electrical and Systems Engineering from the University of Connecticut. He is presently an Associate Professor in the Department of Electrical and Computer Engineering at the University of Tennessee, Knoxville. Dr. Islam is leading the research efforts of the Analog VLSI and Devices Laboratory at the University of Tennessee. His research interests are design, modeling and fabrication of microelectronic/optoelectronic devices, molecular scale electronics and nanotechnology, biomicroelectronics and monolithic sensors. Dr. Islam has numerous publications in technical journals and conference proceedings in the areas of semiconductors devices and circuits. Benjamin J. Blalock received his B.S. degree in electrical engineering from The University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees, also in electrical engineering, from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering at The University of Tennessee where he directs the Integrated Circuits and Systems Laboratory (ICASL). His research focus there includes analog IC design for extreme environments (both wide temperature and radiation immune), multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, mixed-signal/mixed-voltage circuit design for systems-on-a-chip, and bio-microelectronics. Dr. Blalock has co-authored over 60 published refereed papers. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems Inc.     

Accurate extraction of maximum current densities from the layout

A module for efficient extraction of maximum current densities from the layout has been developed and implemented within the CAD package PARIS. The corner-rounding dependence on technology parameters, such as numerical aperture and acid/base diffusion length, was simulated. A combination of classical and meshless FEM was used to obtain accurate results taking the simulated realistic shapes of the corners into account.