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介绍了低压大功率变频调速节能系统在研发和使用中经常遇到的问题和故障。通过分析,找出问题所在,从而制定出解决问题的相关措施。 相似文献
13.
Brent J. Maundy Ivars G. Finvers Peter Aronhime 《Analog Integrated Circuits and Signal Processing》2002,32(2):157-168
Two variants of a new current feedback amplifier (CFA) are presented in this paper. These CFAs are realized in CMOS technology and both are capable of working at low voltages. It is shown that one circuit performs better than the other by virtue of an increased impedance at its Z terminal achieved through the use of additional transistors. Analysis of both variants of the current conveyor and buffer that form the current feedback amplifier gives an insight into the location of primary poles and zeros of the CFAs. Simulation results indicate an overall gain bandwidth product in excess of 59 MHz and 102 MHz for each circuit at a gain of –10 and with a 3.3 V supply. Experimental results from a chip fabricated in a 0.35 m CMOS technology agree closely with the simulation results. 相似文献
14.
Mohammad A. Adeeb Hung Nguyen Syed K. Islam Mo Zhang 《Analog Integrated Circuits and Signal Processing》2006,47(3):355-363
A low-power low-voltage analog signal processing circuit has been designed, fabricated, and tested. The circuit is capable
of processing an analog sensor current and producing an ASK modulated digital signal with modulating signal frequency proportional
to the sensor current level. An on-chip regulator has been included to stabilize the supply voltage received from an external
RF power source. The circuit can operate with a power supply as low as 1 V and consumes only about 20 μW of power, which is
therefore very suitable for implantable biomedical applications. The whole chip was laid out and fabricated in a 0.35 μm bulk
CMOS technology. Experimental results show good agreement with the simulation results. 相似文献
15.
本文设计了一种低压低功耗CMOS折叠一共源共栅运算放大器.该运放的输入级采用折叠-共源共栅结构,可以优化输入共模范围,提高增益;由于采用AB类推挽输出级,实现了全摆幅输出,并且大大降低了功耗.采用TSMC 0.18μm CMOS工艺,基于BSIM3V3 Spice模型,用Hspice对整个电路进行仿真,结果表明:与传统结构相比,此结构在保证增益、带宽等放大器重要指标的基础上,功耗有了显著的降低,非常适合于低压低功耗应用.目前,该放大器已应用于14位∑-△模/数转换电路的设计中. 相似文献
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针对《低压配电设计规范》(GB50054-95)中第4.3.4条过负荷保护公式如何理解的问题,通过分析国内外相关标准规范,并结合计算实例,说明低压配电线路过负荷保护公式的含义和使用。 相似文献
18.
Vitor R. ManfrinatoLin Lee Cheong Huigao DuanDonald Winston Henry I. SmithKarl K. Berggren 《Microelectronic Engineering》2011,88(10):3070-3074
We fabricated 9-30 nm half-pitch nested Ls and 13-15 nm half-pitch dot arrays, using 2 keV electron-beam lithography with hydrogen silsesquioxane (HSQ) as the resist. All structures with 15 nm half-pitch and above were fully resolved. We observed that the 9 and 10-nm half-pitch nested Ls and the 13-nm-half-pitch dot array contained some resist residues. We obtained good agreement between experimental and Monte-Carlo-simulated point-spread functions at energies of 1.5, 2, and 3 keV. The long-range proximity effect was minimal, as indicated by simulated and patterned 30 nm holes in negative-tone resist. 相似文献
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This article presents the design of a high output compliance, very-high output impedance single-ended charge pump implemented using a new low-voltage current mirror. The output current is sampled and a feedback loop forces it to be equal to the desired reference current. This results in a very-high output impedance over a very wide output voltage range, accurate Up/Down current matching, and low transient glitches. The proposed charge pump was implemented using STMicroelectronics 1-V 90-nm CMOS process. Simulations using Spectre show that the Up/Down output currents remain constant and matched within 1% over a charge pump output voltage ranging from 119 to 873 mV. Monte Carlo process variations and mismatch simulations indicate that the 1-σ standard deviation between the Up and Down current components is , or 6.8% of the nominal charge pump current at either end of the output voltage range. 相似文献