高温正向栅电流下Ti/Pt/Au栅SiC MESFET的栅退化机理

SiC MESFET器件的性能强烈依赖于栅肖特基结的特性,而栅肖特基接触的稳定性直接影响其可靠性.针对SiC MESFET器件在微波频率的应用中射频过驱动导致高栅电流密度的现象,设计了两种栅极大电流的条件,观察栅肖特基接触和器件特性的变化,并通过对试验数据的分析,确定了栅的寄生并联电阻的缓慢退化是导致栅肖特基结和器件特性退化,甚至器件烧毁失效的主要原因.     

A Wave Approach to Signal and Noise Modeling of Dual-Gate MESFET

A new procedure for signal and noise modeling of dual-gate MESFET is described in this paper. The small-signal model is based on two cascoded single-gate MESFET intrinsic equivalent circuits embedded in a network representing device parasitics. The wave interpretation of noise is used for defining the noise parameters of each single gate MESFET. Applying this approach, a CAD oriented procedure for extracting the dual-gate MESFETmodel parameters as well as the noise wave temperatures is developed. Modeled scattering and noise parameter characteristics are comparedto the measured ones and quite a good agreement is observed.     

多栅GaAs MESFET开关的结构设计

论述了多栅开关的结构和特点.针对多栅开关器件结构设计中的参数栅栅间距的选取作了分析,确定当栅栅间距等于源漏间距对栅数的平均值时,开关性能最优,并在实验中得到验证     

Improved multi-recessed 4H–SiC MESFETs with double-recessed p-buffer layer

An improved multi-recessed 4H–SiC metal semiconductor field effect transistor (MRD-MESFET) with double-recessed p-buffer layer (DRB-MESFET) is proposed in this paper. By introducing a double-recessed p-buffer layer, the gate depletion layer is further modulated, and higher drain saturation current and DC transconductance are obtained compared with the MRD-MESFET. The simulations show that the drain saturation current of the DRB-MESFET is about 42.4% larger than that of the MRD-MESFET. The DC transconductance of the DRB-MESFET is almost 15% higher than that of the MRD-MESFET and very close to that of double-recessed structure (DR-MESFET) at the bias conditions of V_gs=0 V and V_ds=40 V. The proposed structure has an improvement of 26.1% and 74.2% in the output maximum power density compared with that of the MRD-MESFET and DR-MESFET, respectively. In the meanwhile, the proposed structure possesses smaller gate-source capacitance, which results in better RF characteristics.     

High Performance β-Ga2O3 Schottky Barrier Transistors with Large Work Function TMD Gate of NbS2 and TaS2

Gallium trioxide, β-Ga₂O₃, has been recently studied due to its promising semiconducting properties as active material in transistors or Schottky diodes. Transistors with β-Ga₂O₃ channels are mostly metal oxide field effect transistors (MOSFET), and they show very negative threshold voltages (V_th) in general. Metal semiconductor field effect transistors (MESFETs) with top gate are also reported with less negative V_th. Still, β-Ga₂O₃ MESFETs are only a few. Here, bottom gate architecture β-Ga₂O₃ MESFETs using transition metal dichalcogenide (TMD) NbS₂ and TaS₂ are reported. Due to the large work functions of those metallic TMDs, the MESFETs display minimum subthreshold swing of 61 mV dec⁻¹, small V_th of −1.2 V, minimum OFF I_D of ≈100 fA, and maximum ON/OFF current ratio of ≈10⁸. Both β-Ga₂O₃ Schottky diodes with TaS₂ and NbS₂ display good junction stability even after 300 °C measurements in 10 mTorr vacuum. When the β-Ga₂O₃ MESFET with TaS₂ gate is integrated as a switching FET into an organic light emitting diode (OLED) circuit, it demonstrates long-term leakage endurance performance, maintaining an OLED brightness higher than 58% of the initial intensity after 100 s passes since the ON-switching point, which is even superior to the performance of conventional a-IGZO MOSFET switch.     

A novel 4H-SiC MESFET by lateral insulator region to improve the DC and RF characteristics

In this paper, a novel recessed gate metal–semiconductor field-effect transistor (RG-MESFET) is presented by modifying the depletion region and the electric field. The proposed structure improves the breakdown voltage, drain current and high frequency characteristics by embedding a lateral insulator region between drain and gate while is placed laterally into the metal gate and a silicon well exactly under the insulator region. We called this new structure as modified recess gate MESFET (MRG-MESFET). The radio frequency and direct current (DC) characteristics of the proposed structure is studied using numerical simulations and compared with a conventional MESFET (C-MESFET). The breakdown voltage, drain current DC transconductance and maximum power density of the proposed structure increase by 27%, 16.5%, 15% and 48%, respectively, relative to the C-MESFET. Also, the gate-source capacitance and the minimum noise figure of the proposed structure improve relative to the C-MESFET. The proposed structure can be used for high breakdown voltage, high saturation drain current, high DC transconductance, high power, high frequency, and low noise applications.     

Frequency dispersion investigation of output reactance and capacitance in GaAs MESFETs by means of dielectric loss tangent consideration

The aim of this article is to investigate the effect of dielectric loss tangent on frequency dispersion of output reactance and capacitance in GaAs MESFETs. For this purpose, measurements of output impedance modulus and phase have been carried out within a frequency range of 10 Hz to 10 kHz, and various voltage values of gate-source (V_gs=0, -0.2, -0.3, -0.35, -0.4, -0.45, -0.5 and -0.6 V) and drain-source (V_ds=0.7, 0.9, 1, 1.5 and 2 V) Based on the concept of complex permittivity of semiconductor material, complex capacitance is used to analyze and simulate frequency dispersion of output reactance and capacitance of GaAs MESFETs. The results show that conductor losses which dominate the dielectric loss tangent are attributed to trapping mechanisms at the interface of devices; so they influence the frequency dispersion of output reactance and capacitance in particular at low frequencies. This reveals that frequency dispersion of these parameters is also related to dielectric loss tangent of semiconductor materials which affects the response of electronic devices according to frequency variation.     

4H-SiC MESFET的反应离子刻蚀和牺牲氧化工艺研究

对于栅挖槽的4H-SiCMESFET,栅肖特基接触的界面经过反应离子刻蚀,界面特性对于肖特基特性和器件性能至关重要。反应离子刻蚀的SiC表面平滑度不是很好,刻蚀损伤严重。选择合适的RIE刻蚀条件减小刻蚀对半导体表面的损伤;利用牺牲氧化改善刻蚀后的表面形貌,进一步减小表面的刻蚀损伤。工艺优化后栅的肖特基特性有了明显改善,理想因子接近于1。制成的4H-SiCMESFET直流夹断特性良好,饱和电流密度达到350mAmm。     

SiCOI MESFET的特性分析

提出了一种新的器件结构-SiCOI结构,即硅衬底上外延SiC制造MESFET器件,并建立了SiCOI MESFET器件结构与模型。使用ISE-TCAD二维器件仿真软件,对SiCOI MESFET的电学特性进行模拟分析。结果表明,通过调整器件结构参数,例如门极栅长、有源层掺杂浓度、有源区厚度等,对器件转移特性、输出特性有较大影响。同时,还对SiCOI MESFET器件的击穿特性进行了模拟。这些电学特性数据为进一步设计及优化SiCOI MESFET器件提供理论基础。     

不同工艺下GaAs MESFET阈值电压均匀性的研究

分别采用挖槽工艺和平面选择离子注入自隔离工艺对 Ga As MESFET Vth(阈值电压 )均匀性进行了研究。结果表明 ,采用平面工艺方法获得的 Ga As单晶 MESFET Vth均匀性与采用挖槽工艺相比 ,更能反映单晶材料质量的实际情况 ,Ga As单晶 MESFET Vth均匀性研究宜采用平面工艺