中频感应器电气参数计算分析

单匝感应器的电阻、电抗、功率因数、品质因数以及效率等参数,对合理选择中频电源有很大的影响。本文给出了空心异型铜质单匝中频感应器电气参数的计算结果,并根根计算结果制成的水冷单匝感应器,在电流密度为70A/mm~2条件下投入工业运行,效果良好。     

基于物理结构的电感杂散电容计算方法

介绍了一种计算电感杂散电容的解析方法,以电感的物理结构为基础,将电感绕组分割成彼此相同的基本单元,求出基本单元的电容,即可获得单层、多层电感的电容。实验证明计算的精确度令人满意,可对电感的设计和仿真提供帮助。     

Parasitic resistance current sensing topology for coupled inductors

Traditional current sensing topology based on inductor equivalent series resistance fails to extract phase currents for coupled inductors due to the presence of the magnetising inductance. This article proposes a new direct-current resistance current sensing topology for coupled inductors. By implementation of a simple resistor-capacitor network, the proposed topology can preserve the coupling effect between phases. As a result, real phase inductor currents and total current can be sensed. Detailed mathematical analysis and design equations are presented in this article. Sensitivity and mismatch issues are addressed. Experimental results show that the proposed topologies are able to extract phase current as well as total current with acceptable accuracy.     

引出结构对叠层片式电感器可靠性影响的研究

叠层片式电感器(MLCI)其引出结构在热应力冲击下,可能会形成开路,降低了MLCI的可靠性,进而影响到电子线路的整体功能。针对实际应用过程中一例叠层片式电感器(型号CH1608H22N)的失效,采用X射线检查、金相检查等分析方法对电感器的失效机理进行了分析。结果表明引出电极与内电极结合部位的热致失效导致了开路,进而研究了引出结构对MLCI可靠性的影响,设计出了一种新的圆弧型引出结构,通过实验验证该结构的耐流特性比直角型引出结构的提高了50%,产品可靠性得以改善。     

A New CMOS Current-Mode Multiplexer for l0 Gbps Serial Links

This paper presents an in-depth study of the pros and cons of voltage-mode multiplexers for Gbps serial links and exploits the advantages of multiplexing in current domain. In addition, it proposes a new fully differential CMOS current-mode multiplexer where a high multiplexing speed is achieved by multiplexing at a low-impedance node. Multiplexing speed is further improved by inductive shunt peaking with active inductors. The differential configuration of the multiplexer minimizes the effect of common-mode disturbances, particularly those coupled from the power and ground rails. The flow of the output currents in the opposite directions minimizes the effect of electro-magnetic interference from channels, making the multiplexer particularly attractive for high-speed data transmission over long interconnects and printed-circuit-board (PCB) traces. The proposed multiplexer draws a constant current from the supply voltage, thereby minimizing both switching noise and noise injected to the substrate. A fully differential CMOS current-mode 8-to-l multiplexer has been implemented in TSMC’s 1.8 V 0.18 μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3v device models. Simulation results demonstrate that the multiplexer offers sufficiently large eye-opening when multiplexed at 10 Gbps.Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. Since 2002, she has been a research assistant with the System-on-Chip research lab of Ryerson University. She is currently a M.A.Sc candidate under the supervision of Dr. Fei Yuan in the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada. Her research interests are in analog CMOS circuit design for high-speed data communications. She was awarded the Ontario Graduate Scholarship (OGS) in 2003–2005 for academic excellence.Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc. degree in chemical engineering and PhD. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively.During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching” award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

Nonlinear characteristics of on-chip spiral inductors under high RF power

This paper explores silicon CMOS on-chip spiral inductors performance degradation under high RF power. A novel methodology to calibrate and characterize on-chip spiral inductor with large signal inputs (high/medium power) is presented. Experiments showed 12% degradation of quality factor in a particular inductor design when 34 dBm RF power was applied. The degradation of quality factor of inductor can be attributed to a local self heating effect. Thermal imaging of such an inductor under high RF power validates the hypothesis.     

Application-aware virtual paths insertion for NOCs

Network-on-chip (NoC) has rapidly become a promising alternative for complex system-on-chip architectures including recent multicore architectures. Additionally, optimizing NoC architectures with respect to different design objectives that are suitable for a particular application domain is crucial for achieving high-performance and energy-efficient customized solutions. Despite the fact that many researches have provided various solutions for different aspects of NoCs design, a comprehensive NoCs system solution has not emerged yet. This paper presents a novel methodology to provide a solution for complex on-chip communication problems to reduce power, latency and area overhead. Our proposed NoC communication architecture is based on setting up virtual source–destination paths between selected pairs of NoCs cores so that the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these virtual paths. In this scheme, the paths are constructed for an application based on its task-graph at the design time. After that, the run time scheduling mechanism is applied to improve the buffer management, virtual channel and switch allocation schemes and hence, the constructed paths are optimized dynamically. Moreover, in our design the router complexity and its overheads are reduced. Additionally, the suggested router has been implemented on Xilinx Virtex-5 FPGA family. The evaluation results captured by SPLASH-2 benchmark suite reveal that in comparison with the conventional NoC router, the proposed router takes 25% and 53% reduction in latency and energy, respectively besides 3.5% area overhead. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and total power consumption with negligible area overhead.     

一种片上集成模拟信号累加结构的CMOS-TDI传感器噪声建模与分析

提出了一种16级片上模拟累加电路结构以实现时间延迟积分(TDI)功能,累加单元以电荷放大器为基础.为了获得更好的噪声性能,对电路结构的模拟信号链路进行了噪声分析,给出了适用于TDI累加的热噪声模型.分析表明,主要随机热噪声根据累加电路工作的状态不同可以分成电荷传输噪声和直接采样噪声两部分.给出每部分噪声与电路增益大小的关系和相应的抑制方法.采用0. 5μm标准CMOS工艺实现了16×256级CMOS-TDI探测器芯片,流片的测试结果表明16级TDI可以获得11. 22 d B的SNR提升.     

An wide-range tunable on-chip radio-frequency LC-tank formed with a post-CMOS-compatible MEMS fabrication technique

An on-chip-micromachined tunable LC-tank, which consists of a metal inter-digitated variable capacitor and a metal solenoid inductor, is developed for wide-range radio-frequency (RF) tuning in multi-GHz band. A low-temperature metal MEMS process is developed to on-chip fabricate the passives. The process can be used for post-CMOS-compatible integration with RF ICs. Both the varactor and the inductor are suspended with a gap from the low-resistivity silicon wafer (i.e. standard CMOS wafer) for effectively depressing RF loss. The fabricated variable capacitor part, the inductor part and the whole tunable LC resonator are sequentially tested, finally resulting in a wide resonance-frequency tuning range of 72% (between about 3.5 and 6.0 GHz) under a low tuning voltage range of 0-4 V, while the Q-factor ranged within 23 and 8.