Efficiency of magnetic coupled boost DC‐DC converters mainly dedicated to renewable energy systems: influence of the coupling factor

This paper presents a specific analysis of an individual basic magnetically coupled direct current‐to‐direct current (DC–DC) converter specially designed for integration in a distributed architecture of renewable energy generators for smart grid applications. In such distributed architecture dedicated for renewable energy, parallel high‐voltage DC presents many advantages over the classical centralized one. We show that in such setup, high voltage can be advantageously produced using a specific magnetically coupled boost converter, and we point out the influence of the coupling factor, generally considered equal to one, on the overall performance of the converter and on the global energy efficiency of the installation. In this study, the generalized concepts of system energy parameters of DC–DC converters are introduced and applied to the transient analysis. Consequently, the operation of a magnetic coupled DC–DC converter with a recovery stage is modeled. The simulation results are compared with those of the behavioral study, deduced from the model pointing out the large influence of the coupling factor value on the global behavior and mainly on the value of the recovery voltage, in all the various parts of the switching cycle. The renewable energy generator operating parameters, such as current and voltage values, can then be predicted in a more useful way to compute new similar DC–DC converter systems. Copyright © 2014 John Wiley & Sons, Ltd.     

Quantifying the effect of local interconnects on on-chip power distribution

Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.     

一种改进的片内ESD保护电路仿真设计方法

对现有的片内ESD保护电路仿真设计方法进行了改进,使之适用于深亚微米工艺.文中设计了新的激励电路以简化仿真电路模型;增加了栅氧化层击穿这一失效判据;使用能量平衡方程描述深亚微米MOSFET的非本地输运,并对碰撞离化模型进行了修正;使用蒙特卡罗仿真得到新的电子能量驰豫时间随电子能量变化的经验模型.最后使用文中改进的仿真设计方法对一个ESD保护电路进行了设计和验证,测试结果符合设计要求.     

单晶硅微构件力学特性片上测试系统

设计一种集成静电梳状驱动器和测试结构，专用于单晶硅微构件断裂、疲劳性能测试的片上测试系统。详细介绍测试系统的结构和工作原理。对静电梳状驱动器的驱动电压一驱动力关系、结构刚度以及谐振频率进行计算。利用MEMS（micro-electro-mechanical system）体硅工艺制造该测试系统，加工得到的测试系统在显微镜工作台上进行静态和动态弯曲实验，并将实验结果与ANSYS分析结果进行对比。结果表明，该测试系统性能稳定，能够实现对单晶硅微构件的弯曲断裂和疲劳测试。     

航空相机扫描像移片上补偿技术

查打一体化是当前航空相机的一个主要发展方向,其中一项关键技术为扫描像移的动态、高精度补偿.基于面阵探测器的时间延迟积分(TDI)扫描像移补偿方式相比于光机式的像移补偿方式具有天然的优势,然而当前的面阵探测器TDI像移补偿精度是像素级的,进一步提高查打一体化相机分辨率遇到了瓶颈.针对于此本文首先介绍了查打一体化航空相机工作原理,然后针对帧转移CCD的特性建立了电荷行间转移的数学模型与电荷转移像移的调制传递函数模型,在此基础上提出了一种查打一体化航空相机扫描像移的片上补偿方法,采用该方法可将西相位面阵TDI CCD的像移补偿精度提高至1/2φ像元.最后搭建了实验平台并给出了二、三、四相位面阵TDI CCD电荷转移像移对遥感图像质量的影响,同时也证明了提出的方法能够显著提高图像质量.     

中频感应器电气参数计算分析

单匝感应器的电阻、电抗、功率因数、品质因数以及效率等参数,对合理选择中频电源有很大的影响。本文给出了空心异型铜质单匝中频感应器电气参数的计算结果,并根根计算结果制成的水冷单匝感应器,在电流密度为70A/mm~2条件下投入工业运行,效果良好。     

Novel efficient method for inductance calculation of inductors with optimized layout

In this article, we consider the computing of conformal modules and their application for inductance calculation of spiral inductors with optimized layout. We present a novel and efficient method for inductance and quality factor calculation of inductors with a variable conductor width. The computed inductance is compared with earlier published experimental data and very good agreement is achieved. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip

In multiprocessor system-on-chip, tasks and communications should be scheduled carefully since their execution order affects the performance of the entire system. When we implement an MPSoC according to the scheduling result, we may find that the scheduling result is not correct or timing constraints are not met unless it takes into account the delays of MPSoC architecture. The unexpected scheduling results are mainly caused from inaccurate communication delays and or runtime scheduler’s overhead. Due to the big complexity of scheduling problem, most previous work neglects the inter-processor communication, or just assumes a fixed delay proportional to the communication volume, without taking into consideration subtle effects like the communication congestion and synchronization delay, which may change dynamically throughout tasks execution. In this paper, we propose an accurate scheduling model of hardware/software communication architecture to improve timing accuracy by taking into account the effects of dynamic software synchronization and detailed hardware resource constraints such as communication congestion and buffer sharing. We also propose a method for runtime scheduler implementation and consider its performance overhead in scheduling. In particular, we introduce efficient hardware and software scheduler architectures. Furthermore, we address the issue of centralized implementation versus distributed implementation of the schedulers. We investigate the pros and cons of the two different scheduler implementations. Through experiments with significant demonstration examples, we show the effectiveness of the proposed approach.     

Analytical wide-band modeling of high frequency resistance in integrated spiral inductors

For integrated spiral inductor synthesis, designers and design automation tools require efficient modeling techniques during the initial design space exploration process. In this paper, we introduce an analytical frequency-dependent resistance model for integrated spiral inductors. Based on our resistance formulation, we have developed a systematic technique for creating wide-band circuit models for accurate time domain simulation. The analytical resistance model provides a fast alternative to field solver-based approaches with typical errors of less than 2.6 percent while surpassing the accuracy of several other analytical modeling techniques by an order of magnitude. Furthermore, the wide-band circuit generation technique captures the frequency-dependent resistance of the inductor with typical errors of less than 3.2 percent.     

基于对称螺旋型电感和差分二极管的2.4GHz CMOS正交输出压控振荡器

提出了一种产生2.4GHz正交本地振荡信号的方法.它将LC-VCO和两级环路振荡器两种结构组合起来以实现正交输出的低相位噪声压控振荡器.LC网络是由在片对称螺旋型电感和差分二极管组成的.详细论述了VCO原理及其噪声性能.该电路已经用0.25μm单层多晶、五层金属N阱CMOS数字工艺制作.测量结果表明:它可以提供正交的本地振荡信号,其振荡频率可以在300MHz的范围内调节,当仅对差分输出振荡信号的一端进行测试时,振荡频率为2.41GHz时,去偏移中心为600kHz时的相位噪声为-104.33dBc/Hz.而且,它能在很低的电源电压下工作,功耗也很低,所以,它在集成收发机中将得到广泛的应用.