De-embedding method for on-wafer RF CMOS inductor measurements

In this work, an accurate de-embedding method for on-wafer RF measurements of CMOS large area devices like the inductors is presented. The method uses distributed and lumped-element models to represent the parasitic elements. The interconnect parasitics are calculated using the transmission line theory. The proposed method is compared to existing de-embedding methods. The validity of the method is checked with the DC resistance value of the interconnects as calculated from the layout and as extracted from measurements, as well as with inductance results of the fabricated inductor, extracted from measurements and from electromagnetic simulations. On-wafer S-parameter measurements have been taken from a test chip up to 20 GHz.     

RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique

The problem of parameter variability in RF and analog circuits is escalating with CMOS scaling. Consequently every RF chip produced in nano-meter CMOS technologies needs to be tested. On-chip Design for Testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, Artificial Neural Networks (ANN) are employed as a multivariate regression technique to architect a RF calibration scheme for DfT chain using DC- instead of RF (GHz) stimuli. The use of DC stimuli relaxes the package design and on-chip routing that results in test cost reduction. A DfT circuit (RF detector, Test-ADC, Test-DAC and multiplexers) designed in 65 nm CMOS is used to demonstrate the proposed calibration scheme. The simulation results show that the cumulative variation in a DfT circuit due to process and mismatch can be estimated and successfully calibrated, i.e. 25% error due to process variation in DfT circuit can be reduced to 2.5% provided the input test stimuli is large in magnitude. This reduction in error makes parametric tests feasible to classify the bad and good dies especially before expensive RF packaging.     

A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm².     

A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs

Recent studies have shown that On-Chip Interconnects (OCI) architecture represents one of the most important component that determines the overall performance of future System-on-Chip (SoC). In order to improve the performance of a specific SoC application domain, the OCI architecture must be optimized at design/run time. Different OCI-based architectures have been recently proposed, the most recent ones are fractal-based or self-similar topologies. In this paper, we present a customization approach by adding strategic links targeted to match large application workload. Simulations results show the effectiveness of this method to achieve better performance compared to the basic OCI architectures. Furthermore, fractal based OCIs perform well almost in all traffic patterns because of their attractive properties.     

An Investigation of Size‐Reduction Effects in High Power Density Boost Converters with a Magnetic Coupling

The dc–dc converter using integrated magnetic components that may achieve high power density has gained attention in environmentally friendly cars such as electric vehicles and hybrid electric vehicles. This paper focused on interleaved boost converters using close‐coupled inductors (CCIs) and loose‐coupled inductors (LCIs) that are the integrated magnetic components. Following, detailed electromagnetically analysis for these circuit types were conducted in order to calculate volume of inductors and capacitors that are occupied the large part of space in the converters. The total volume of inductors and capacitors in these circuits were demonstrated clearly through comparison with conventional circuits such as an interleaved boost converter and a single‐phase boost converter. As a result, it became clear that interleaved boost converter using LCIs was effective for miniaturization of total volume. Furthermore, duty ratio of the minimum volume of CCI method is different from the duty ratio of the minimum volume of LCI method.     

An eclectic approach to design tunable amplifiers

Broadband amplifiers that can accommodate commercial communication standards such as GSM, UMTS, Wi‐Fi, and Wi‐Max are extremely important for radio equipment manufacturers. To achieve this coverage, the amplifier should provide high gain and efficiency over a band from 800 to 5200 MHz. Although there are transistor devices that have cut‐off frequencies well over these frequencies, amplifiers covering such a broad‐bandwidth are difficult to design due to the requirement of broadband matching networks. In this work, design of broadband tunable matching networks is investigated using Real Frequency Direct Computational Technique (RF‐DCT). In order to be able to work on sample structures, impedance transforming filters are chosen and a broadband tunable matching network has been designed. Implementation of tunable inductors is investigated and the performance of a tunable matching network using tunable inductors and capacitors is demonstrated. Eventually a broadband frequency tunable amplifier has been designed using the tunable inductor concept. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.     

20CrMo抽油杆串联感应加热调质后的组织与性能

研究了２０ＣｒＭｏ钢Ｄ级重载抽油杆串联感应加热快速调质过程中淬，回火感应器参数的确定及加热功率，温度，进给速度对能耗和调质后组织与性能的影响规律；分析了快速调质工艺的高温回火机制。结果表明：串联感应加热快速调质能明显提高抽油杆的强韧性和拉伸疲劳力，显著地提高生产效率大量节约能源。     

一款基于65nm CMOS工艺的高效率50GHz 压控振荡器及其电感耦合效应的研究

A 50 GHz cross-coupled voltage controlled oscillator(VCO) considering the coupling effect of inductors based on a 65 nm standard complementary metal oxide semiconductor(CMOS) technology is reported.A pair of inductors has been fabricated,measured and analyzed to characterize the coupling effects of adjacent inductors. The results are then implemented to accurately evaluate the VCO’s LC tank.By optimizing the tank voltage swing and the buffer’s operation region,the VCO achieves a maximum efficiency of 11.4%by generating an average output power of 2.5 dBm while only consuming 19.7 mW(including buffers).The VCO exhibits a phase noise of—87 dBc/Hz at 1 MHz offset,leading to a figure of merit(FoM) of-167.5 dB/Hz and a tuning range of 3.8%(from 48.98 to 50.88 GHz).     

CMOS planar spiral inductor modeling and low noise amplifier design

During this study, various narrowband single-ended inductive source degenerated Low Noise Amplifiers (LNAs) for GSM and S-band low earth orbit (LEO) space applications have been designed, simulated and compared using Mietec CMOS 0.7 μm process and the Cadence/BSIM3v3. To get more realistic results, parasitic effects due to layout have been calculated and added to the simulations. Also, considering the inductive source degenerative topology, most of the attention is given on the modeling of planar spiral inductor by lumped element circuits. Moreover to decrease the substrate effects, the inductors have been surrounded by grounded guard rings and have patterned ground shield (PGS) under them. The simulation results of LNA including the parasitic effects indicate a forward gain of 9 dB with noise figure of 4.5 dB while drawing 18 mW from+3 V supply at 2210 MHz. The area occupied is 1.8 mm×1.6 mm with pads, 1.3 mm×1.2 mm without pads.     

一种超宽带正交调制器片上巴伦的设计

采用0.18 μm GeSi BiCMOS工艺,通过调节中心抽头位置、设计八边形螺旋电感、添加屏蔽层、优化线圈外径与金属线宽等方法,设计了一种平衡性好、插入损耗小的片上巴伦。创新性地在HFSS模型中引入GSG焊盘,避免了去嵌入处理的复杂计算与计算误差。仿真结果表明:在500 MHz频率处,电路的插入损耗为3.5 dB,幅度不平衡度为0.13 dB,相位不平衡度为0.38°;在4 GHz频率处,插入损耗为1.8 dB,幅度不平衡度为1.62 dB,相位不平衡度为2.85°。对样品的S参数幅度及相位进行测试,实测结果与仿真值吻合。该巴伦可应用于500 MHz~4 GHz的超宽带正交调制器中,具有较好的应用前景。