20CrMo抽油杆串联感应加热调质后的组织与性能

研究了２０ＣｒＭｏ钢Ｄ级重载抽油杆串联感应加热快速调质过程中淬，回火感应器参数的确定及加热功率，温度，进给速度对能耗和调质后组织与性能的影响规律；分析了快速调质工艺的高温回火机制。结果表明：串联感应加热快速调质能明显提高抽油杆的强韧性和拉伸疲劳力，显著地提高生产效率大量节约能源。     

一种超宽带正交调制器片上巴伦的设计

采用0.18 μm GeSi BiCMOS工艺,通过调节中心抽头位置、设计八边形螺旋电感、添加屏蔽层、优化线圈外径与金属线宽等方法,设计了一种平衡性好、插入损耗小的片上巴伦。创新性地在HFSS模型中引入GSG焊盘,避免了去嵌入处理的复杂计算与计算误差。仿真结果表明:在500 MHz频率处,电路的插入损耗为3.5 dB,幅度不平衡度为0.13 dB,相位不平衡度为0.38°;在4 GHz频率处,插入损耗为1.8 dB,幅度不平衡度为1.62 dB,相位不平衡度为2.85°。对样品的S参数幅度及相位进行测试,实测结果与仿真值吻合。该巴伦可应用于500 MHz~4 GHz的超宽带正交调制器中,具有较好的应用前景。     

一种RF MEM电感及其LC低通滤波器的模拟和设计

模拟并设计了一种基于表面微机械加工的平面MEM电感,提出了它的等效电路模型并给出模型中参数的提取方法。由模拟结果验证了该等效电路具有较高的精度,误差在8%以内。设计的一个3.6nH的平面MEM电感的品质因数超过20,自谐振频率超过15GHz。由平面MEM电感构成的5阶LC低通滤波器的-3dB带宽为3.7GHz,0~3GHz内的插入损耗低于1dB。     

Nanostructured catalyst with hierarchical porosity and large surface area for on-chip fuel cells

This communication reports the synthesis of mesoporous Pd–Co dendrites with both a unique hierarchical porosity and a large surface area by the combination of electrodeposition and dealloying. The resultant mesoporous dendrites consist of microparticles with a diameter of a few hundred nanometers, and the particles have mesopores with around 10 nm width. The mesoporous dendrites are found to be Pd₈Co₂, to be composed of pure Pd crystalline phases and amorphous Pd–Co phases, and to be covered with Pd-skin layers. This catalyst exhibits a high activity in the oxygen reduction reaction. Thus, this novel catalyst is attractive as a catalyst for on-chip fuel cells, which require catalysts to be deposited precisely onto tiny current collectors.     

Small saturating inductors for more compact switching power supplies

Other than by reducing power, extending battery life in portable microelectronics amounts to increasing power efficiency, which, when coupled with accuracy, translates to increasing filter inductance. The problem with higher inductances is that magnetic cores require more space to prevent the onset of saturation, so accuracy and efficiency (via their need for bulky inductors) hamper the miniaturization benefits gained from chip integration. This paper illustrates the time‐domain and efficiency effects of inductor saturation in switched‐inductor DC–DC converters and shows how they can accommodate saturation (with up to 65% reduction in inductance) with minimal impact on battery life and accuracy. Extending the useful range of an inductor in this fashion not only reduces the printed circuit board (PCB) area and volume to a fraction (e.g., 30–50%) of what an otherwise larger unsaturated inductor would require, but also helps bridge the integration gap that enables practical system‐on‐chip (SoC) implementations. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

交错并联Boost PFC电路的应用研究

详细论述了电感电流断续模式下的Boost PFC交错并联电路,该控制电路能有效减小输入电流纹波和开关器件的电流应力、减小单个电感容量和前级EMI滤波器尺寸,提高PFC电路的功率等级和效率。分析对比了电感电流断续模式下,交错并联Boost PFC电路中分立电感和耦合电感的工作原理。由分析可知,采用电感直接耦合的PFC电路存在电感峰值电流增大,输入电流谐波含量高,功率因数低等问题。采用一种新颖的耦合电感绕线方式,并利用Gyrator-Capacitor法对该耦合方式建立模型,仿真和实验证明这种新颖的电感绕线方式能很好地克服电感直接耦合存在的缺点。     

De-embedding method for on-wafer RF CMOS inductor measurements

In this work, an accurate de-embedding method for on-wafer RF measurements of CMOS large area devices like the inductors is presented. The method uses distributed and lumped-element models to represent the parasitic elements. The interconnect parasitics are calculated using the transmission line theory. The proposed method is compared to existing de-embedding methods. The validity of the method is checked with the DC resistance value of the interconnects as calculated from the layout and as extracted from measurements, as well as with inductance results of the fabricated inductor, extracted from measurements and from electromagnetic simulations. On-wafer S-parameter measurements have been taken from a test chip up to 20 GHz.     

The psi-cube: a bus-based cube-type clustering network for high-performance on-chip systems

This paper proposes a bus-based cube-type network, called psi-cube, that alleviates the two problems, long wires and a limited number of I/O pins, against the on-chip systems through a small diameter and dynamic clusters, respectively. The 2ⁿ-node psi-cube is organized on the sets of node-partitions produced with an extended n-bit Hamming code ψ(n, k) [M. Takesue, Ψ-Cubes: recursive bused fat-hypercubes for multilevel snoopy caches, in: Proceedings of the International Symposium on Parallel Architectures, Algorithms, and Networks, IEEE CS Press, 1999, pp. 62–67] if we connect the nodes in each partition to the bus owned by the leader of the partition. Owing to the routing between the leaders separated by the distance of 1–3, the diameter equals n/2 if n≠2^p − 1 or n/2 otherwise. The maximum bus length is O(2^p−1) or O(2^k−1) when the psi-cube is mapped onto an array. We dynamically produce separate sets of clusters for different off-chip targets such as memory blocks, so the traffic to the leaders of clusters is much smaller than in static clusters fixed in hardware. From simulation results, the psi-cube outperforms over the mesh if the bus delay is less than 4 times the mesh link’s, and the dynamic clusters increase the psi-cube bandwidth by over 60%.     

Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors

This paper explores the suitability of dense circulant graphs of degree four for the design of on-chip interconnection networks. Networks based on these graphs reduce the Torus diameter in a factor , which translates into significant performance gains for unicast traffic. In addition, they are clearly superior to Tori when managing collective communications. This paper introduces a new two-dimensional node’s labeling of the networks explored which simplifies their analysis and exploitation. In particular, it provides simple and optimal solutions to two important architectural issues: routing and broadcasting. Other implementation issues such as network folding and scalability by using hierarchical networks are also explored in this work.     

一种带耦合电感的交错并联型DC/DC变换器研究

在轻负载条件下单组全桥变换器在滞后管关断后存在输出变压器次级短路、初级有环流存在的现象,使得变换器的控制复杂,轻载时变换器效率不高。为了提高大功率变换器性能,解决变压器次级短路问题,提出了一种输出带耦合电感的变换器拓扑,实现了滞后桥臂开关管的零流关断和零压开通。然后,分析了所提出的变换器电路的工作原理,给出了关键参数的设计。最后对变换器进行了实验。实验结果与理论分析一致。