基于物理结构的电感杂散电容计算方法

介绍了一种计算电感杂散电容的解析方法,以电感的物理结构为基础,将电感绕组分割成彼此相同的基本单元,求出基本单元的电容,即可获得单层、多层电感的电容。实验证明计算的精确度令人满意,可对电感的设计和仿真提供帮助。     

桥式电路中不同封装SiC MOSFET串扰问题分析及低栅极关断阻抗的驱动电路

由于SiC MOSFET开关速度较快,使得桥式电路中串扰问题更加严重,这样不仅限制了SiC MOSFET开关速度的提升,也会降低电力电子装置的可靠性。针对SiC MOSFET的非开尔文结构封装和开尔文结构封装的串扰问题分别进行分析,栅漏极结电容的充放电电流和共源寄生电感电压均会引起处于关断状态开关管的栅源极电压变化。提出一种用于抑制串扰问题的驱动电路,该驱动电路具有栅极关断阻抗低、结构简单、易于控制的特点。分析该驱动电路的工作原理,提供主要参数的计算方法。最后通过实验测试了两种结构封装SiC MOSFET的串扰问题,并且对提出的驱动电路进行了实验,验证了其正确性以及对串扰问题的抑制效果。     

四相交错并联双向DC-DC变换器中耦合电感的设计准则

深入研究了四相Buck+Boost交错并联双向DC-DC磁集成变换器运行在Buck模式下的稳态电流纹波和暂态电流响应速度,同时研究了耦合电感的非对称性对变换器性能的影响,通过分析磁集成变换器的占空比和电感耦合系数对稳态电流纹波和暂态电流响应速度的影响,总结出四相Buck+Boost交错并联双向DC-DC非对称磁集成变换器运行在Buck模式下的设计准则,即在设计这种非对称变换器时,利用给出的设计公式和设计区域选择相关参数。最后,通过实验验证了理论分析的正确性。     

Application-aware virtual paths insertion for NOCs

Network-on-chip (NoC) has rapidly become a promising alternative for complex system-on-chip architectures including recent multicore architectures. Additionally, optimizing NoC architectures with respect to different design objectives that are suitable for a particular application domain is crucial for achieving high-performance and energy-efficient customized solutions. Despite the fact that many researches have provided various solutions for different aspects of NoCs design, a comprehensive NoCs system solution has not emerged yet. This paper presents a novel methodology to provide a solution for complex on-chip communication problems to reduce power, latency and area overhead. Our proposed NoC communication architecture is based on setting up virtual source–destination paths between selected pairs of NoCs cores so that the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these virtual paths. In this scheme, the paths are constructed for an application based on its task-graph at the design time. After that, the run time scheduling mechanism is applied to improve the buffer management, virtual channel and switch allocation schemes and hence, the constructed paths are optimized dynamically. Moreover, in our design the router complexity and its overheads are reduced. Additionally, the suggested router has been implemented on Xilinx Virtex-5 FPGA family. The evaluation results captured by SPLASH-2 benchmark suite reveal that in comparison with the conventional NoC router, the proposed router takes 25% and 53% reduction in latency and energy, respectively besides 3.5% area overhead. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and total power consumption with negligible area overhead.     

平面圆形螺旋电感器和变压器的计算机辅助设计

本文在准静态条件下,分析了应用于微波单片集成电路中的圆形螺旋电感器和变压器,举出了它们的等效电路.求得格林函数后利用矩量法求出了圆形微带线上的电流和电荷分布.导出了计算平面圆形螺旋电感器和变压器等电路中各元件数值的公式以及“S”参数表示式.编制了相应的程序.利用这些程序可以分析计算具有任意匝数(包括非整数)和各种几何参数的平面圆形螺旋电感器和变压器.平面圆形螺旋电感器的计算值与实验值比较,最大误差约为5%.     

A New CMOS Current-Mode Multiplexer for l0 Gbps Serial Links

This paper presents an in-depth study of the pros and cons of voltage-mode multiplexers for Gbps serial links and exploits the advantages of multiplexing in current domain. In addition, it proposes a new fully differential CMOS current-mode multiplexer where a high multiplexing speed is achieved by multiplexing at a low-impedance node. Multiplexing speed is further improved by inductive shunt peaking with active inductors. The differential configuration of the multiplexer minimizes the effect of common-mode disturbances, particularly those coupled from the power and ground rails. The flow of the output currents in the opposite directions minimizes the effect of electro-magnetic interference from channels, making the multiplexer particularly attractive for high-speed data transmission over long interconnects and printed-circuit-board (PCB) traces. The proposed multiplexer draws a constant current from the supply voltage, thereby minimizing both switching noise and noise injected to the substrate. A fully differential CMOS current-mode 8-to-l multiplexer has been implemented in TSMC’s 1.8 V 0.18 μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3v device models. Simulation results demonstrate that the multiplexer offers sufficiently large eye-opening when multiplexed at 10 Gbps.Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. Since 2002, she has been a research assistant with the System-on-Chip research lab of Ryerson University. She is currently a M.A.Sc candidate under the supervision of Dr. Fei Yuan in the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada. Her research interests are in analog CMOS circuit design for high-speed data communications. She was awarded the Ontario Graduate Scholarship (OGS) in 2003–2005 for academic excellence.Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc. degree in chemical engineering and PhD. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively.During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching” award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

An wide-range tunable on-chip radio-frequency LC-tank formed with a post-CMOS-compatible MEMS fabrication technique

An on-chip-micromachined tunable LC-tank, which consists of a metal inter-digitated variable capacitor and a metal solenoid inductor, is developed for wide-range radio-frequency (RF) tuning in multi-GHz band. A low-temperature metal MEMS process is developed to on-chip fabricate the passives. The process can be used for post-CMOS-compatible integration with RF ICs. Both the varactor and the inductor are suspended with a gap from the low-resistivity silicon wafer (i.e. standard CMOS wafer) for effectively depressing RF loss. The fabricated variable capacitor part, the inductor part and the whole tunable LC resonator are sequentially tested, finally resulting in a wide resonance-frequency tuning range of 72% (between about 3.5 and 6.0 GHz) under a low tuning voltage range of 0-4 V, while the Q-factor ranged within 23 and 8.     

箝位二极管承受低电压的有源箝位谐振直流环节逆变器

为解决无源箝位谐振直流环节逆变器辅助电路中采用耦合电感辅助换流（即抽头电感法）所引起的箝位二极管两端承受的电压应力过大问题,提出一种箝位二极管承受低电压的有源箝位谐振直流环节逆变器,该逆变器采用有源箝位的方法可使箝位二极管两端承受的最大反向电压不超过直流母线电压的最大值.且该逆变器的辅助谐振电路中只有一个辅助开关器件,箝位电路中无需设置箝位开关,控制简单且硬件成本较低.此外,在箝位电路的作用下可将逆变器的直流母线电压箝位在输入直流电压的1.1~1.3倍,有效地降低了电压应力.以各个阶段下的等效电路为基础,对电路的工作过程进行了分析,并进行了实验验证,实验结果表明开关器件实现了软开关,且在额定功率3kW条件下,逆变器的效率达到96.5%.因此,该拓扑结构能够有效地提高工作效率.     

一种片上集成模拟信号累加结构的CMOS-TDI传感器噪声建模与分析

提出了一种16级片上模拟累加电路结构以实现时间延迟积分(TDI)功能,累加单元以电荷放大器为基础.为了获得更好的噪声性能,对电路结构的模拟信号链路进行了噪声分析,给出了适用于TDI累加的热噪声模型.分析表明,主要随机热噪声根据累加电路工作的状态不同可以分成电荷传输噪声和直接采样噪声两部分.给出每部分噪声与电路增益大小的关系和相应的抑制方法.采用0. 5μm标准CMOS工艺实现了16×256级CMOS-TDI探测器芯片,流片的测试结果表明16级TDI可以获得11. 22 d B的SNR提升.     

一种新型片上全差分电感的设计

提出了一种新型的片上全差分电感结构。电感采用全对称的几何形状,消除了传统差分电感因跳线引起的失配,提高了差分电感的性能。基于TSMC 0.18 μm RF CMOS工艺,对设计的全差分电感进行流片与测量,结果表明,差分电感两端口之间的失配量比传统差分电感下降了28%。