世界三大集成元件新产品工艺技术研发动态

论述集成无源元件的重要作用,简介集成电阻器、集成电容器、集成电感器技术。系统探讨了多层金属化工艺、主要衬底材料、工艺集成规则、集成无源模块组装工艺、设计方法及设计实例等关键工艺技术。     

硅基集成螺旋电感的设计

在电子系统开发过程中应用EDA技术，可使电子工程师在实际电子系统产生之前全面了解系统的功能特性和物理特性，不仅缩短开发时间，也降低开发成本。本文利用Ansoft HFSS9．2三维高频仿真设计软件进行硅基集成螺丝电感的建模和分析。同时通过斯坦福大学Thomas H．Lee教授开发的集成电感计算软件进行验证，实验证明利用EDA软件进行射频IC设计会有效的提高工作的效率。     

无线通信系统中的微尺度射频元件

射频元件微型化是微型无线通信系统发展的关键所在.本文从微机械开关、微机械谐振器、微机械滤波器、微机械天线、微机械电感及电容等多方面,介绍微尺度射频元件的研究和应用现状,并对其发展前景作了展望.     

多层片式电感器介质材料及其工艺的发展现状

综述了近年来国内外多层片式电感器介质材料及其工艺研究的发展现状和方向,介绍了不同的频率段,应选择不同的低烧材料作为器件的介质材料,特别针对有关用于高频ＭＬＣＩｓ的低介瓷的研究进行了详细的介绍．同时概括了多层片式电感器生产的特殊而典型工艺过程．     

半绝缘电压互感器感应电压值的探讨

在引出容升电压概念后,对Ｒ、Ｌ、Ｃ串联电路中容升电压与电源电压角频率的关系进行了分析,并通过国内现有产品研究结果的进一步分析,以ＪＣＣ５－２２０电压互感器为例推导出在２００ＨＺ电源频率下进行耐压试验时的容升电压值,并进而求得在２００ＨＺ电源频率下半绝缘电压互感器的感应电压值。     

An adaptive congestion-aware routing algorithm based on network load for wireless routers in wireless network-on-chip

Wireless Network-on-Chip (WiNoC) is regarded as one of the promising alternative approaches for sorting out the issues of latency and power consumption in the conventional Network-on-Chip (NoC). Despite the additional bandwidth of wireless channels on a chip, wireless routers (WRs) are prone to congestion in WiNoC due to the limited number of wireless channels on a chip and the shared use of these channels among all the cores. In this paper, an adaptive congestion-aware routing algorithm consistent with traffic load is proposed for solving the congestion problem of WRs. The proposed algorithm selects source-destination pairs with the longest wired hop distance for using wireless channels. The number of selected packets is determined based on the wireless channel bandwidth and the network traffic load. Simulation results show up to 65% latency improvement, 16% wired/wireless link utilization improvement and a saturation throughput increase of approximately 11%.     

Step‐up/step‐down DC‐DC converter with near zero input/output current ripples

A novel single switch two diode wide conversion ratio step down/up converter is presented. The proposed converter is derived from the conventional single‐ended primary inductor converter (SEPIC) topology, and it can operate as a capacitor‐diode voltage multiplier, which offers simple structure, reduced electromagnetic interference (EMI), and reduced semiconductor voltage stress. The main advantages of the proposed converter are the continuous input/output current, higher voltage conversion ratio, and near‐zero input and output current ripples compared with the conventional SEPIC converter. The absence of both a transformer and an extreme duty cycle permits the proposed converter to operate at high switching frequencies. Hence, the overall advantages will be: higher efficiency, reduced size and weight, simpler structure and control. The theoretical analysis results obtained with the proposed structure are compared with the conventional SEPIC topology. The performance of the proposed converter is verified through computer simulations and experimental results. Copyright © 2012 John Wiley & Sons, Ltd.     

Analysis of Differences in Inductance of Ni-Cu-Zn Ferrite Chip Inductors during the Plating Process

Although plating is a necessary process for SMT components, it alters the magnetic characteristics and inductance level of Ni-Cu-Zn ferrite components. The results of this work show that the following three factors in plating affect these components, and the effects are different for Ni- and Sn-plating： （1） Plating layers exert stresses and react with the residual stress of components to change the inductance level, and the effect of the tin layer is greater than that of the nickel one; （2） The plating current induces a magnetic field inside the components directly and indirectly, and this remains as remanence inside the components and reduces the inductance level, and the effect level of Ni-plating is greater than that of Sn-plating; （3） The plating solution corrodes the interface of the termination and ferrite core of the components to release the residual stress, and causes an increase in inductance, and the effect of Sn-plating is greater than that of Ni-plating. In addition, the inductance level is the result of the net effect of these three factors, and if the sintering temperature is increased to change in the type of residual stress, the net effect will be changed.     

Effect of boron substitution on the properties of NiZnCu ferrite for multilayer chip inductors

The initial permeability of the toroidal core sample with boron substituted NiZnCu ferrite (Ni_0.36Zn_0.44Cu_2.2Fe_1.96 − xB_xO₄(x = 0.0, 0.2, 0.4, 0.6, and 0.8)) which was annealed at 900 °C for 2 h decreased from 162.4 to 123.2 as boron concentration x is increased from 0.2 to 0.8. The quality factor and density of 0.2 mol% boron substituted NiZnCu ferrites sintered at 900 °C for 2 h was about 240.0 and 4.84 g/cm³, respectively. The density, shrinkage and saturation magnetization were increased with increasing annealing temperature. It was shown that the boron substituted NiZnCu ferrite systems were promising as a high quality factor material in the fabrication of multilayer chip inductors (MLCIs).     

无线NoC研究与进展

分析了无线NoC的一般结构,对两种典型拓扑结构及其相关特性进行了比较,并对无线NoC涉及到的关键通信机制,特别是片上天线、路由及通信协议对其性能的影响进行了讨论,最后对未来无线NoC的技术热点及难点问题进行了总结和展望。