An optimal scheduling algorithm for testing interconnect using boundary scan

Systems will soon be built with ICs that conform with the IEEE 1149.1 boundary scan architecture. Due to the hierarchical nature of such systems, they may contain many boundary scan chains. These chains can be used to test the system, subsystem, and board interconnect. To reduce test time, the application of test vectors to these scan chains must be carefully scheduled. This article deals with problems related to finding an optimal schedule for testing interconnect. This problem is modeled using a directed graph. The following results are obtained: (1) upper and lower bounds on interconnect test time; (2) necessary and sufficient conditions for obtaining an optimal schedule when the graph is acyclic; (3) sufficient condition for obtaining an optimal schedule when the graph is cyclic; and (4) an algorithm for constructing an optimal schedule for any graph.This work was supported by Defense Advanced Research Projects Agency and monitored by the Office of Naval Research under contract No. N00014-87-K-0861. The views and conclusions contained in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U.S. Government.     

高速电路平行互连线时延估算与数值分析

利用数值方法分析了0．25μm工艺条件之下双平行线以及三平行线最坏情况下的时间延迟，得到了考虑驱劝电阻以及终端负载影响的时间延迟简单经验计算公式。该公式比文献上已有公式的适应范围更广，与Hspice精确仿真结果的误差在10％以内。     

开路缺陷的软故障关键面积研究

从软故障的产生机制出发,研究了软故障的作用模式.为了计算软     

埋入无源元件集成的高密度印制板

概述了Motorola的埋入PTF电阻、CFP电容和螺旋电感等无源集成的高密度印制板和埋入无源集成技术。     

Effect of manganese addition on reactive evaporation of chromium in Ni-Cr alloys

Chromium is used as an alloy addition in stainless steels and nickel-chromium alloys to form protective chromium oxide scales. Chromium oxide undergoes reactive evaporation in high-temperature exposures in the presence of oxygen and/or water vapor. Deposition of gaseous chromium species onto solid oxide fuel-cell electrodes can reduce the efficiency of the fuel cell. Manganese additions to the alloy can reduce the activity of chromium in the oxide, either from solid solution replacement of chromium with manganese (at low levels of manganese) or from the formation of manganese-chromium spinels (at high levels of manganese). This reduction in chromium activity leads to a predicted reduction in chromium evaporation factors as much as 35 at 800 °C and 55 at 700 °C. Quantifying the effects of manganese additions on chromium evaporation should aid alloy development of metallic interconnects and balance-of-plant alloys. This paper was presented at the ASM Materials Solutions Conference & Show held October 18–21, 2004 in Columbus, OH.     

Characterization and performance of (La,Ba)(Co,Fe)O3 cathode for solid oxide fuel cells with iron–chromium metallic interconnect

(La_0.6Ba_0.4)(Co_0.2Fe_0.8)O₃ (LBCF) is synthesized by a sol–gel method as a Cr-tolerant cathode for intermediate-temperature solid oxide fuel cells (ITSOFCs). The electrochemical performance and Cr deposition process for the O₂ reduction reaction on LBCF cathodes in the presence and absence of a Fe–Cr alloy interconnect are investigated in detail, in comparison with a (La,Sr)(Co,Fe)O₃ (LSCF) electrode. Cr deposition occurs for the O₂ reduction reaction on LBCF electrodes in the presence of Fe–Cr alloy. Very different from that observed for the reaction on the LSCF cathode, Cr deposition on the LBCF electrode/gadolinia-doped ceria (GDC) electrolyte system is very small and shows little poisoning effect for O₂ reduction on LBCF electrode. The results demonstrate that the LBCF electrode has a high resistance towards Cr deposition and high tolerance towards Cr poisoning.     

一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法. 该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点，将它们混合插入到连线的合适位置，从而降低互连的延时和功耗. 模拟结果表明，该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

多变量灰色模型MGM（1,n）在电磁继电器特性参数分析中的应用研究

触点电接触特性参数的变化可以反映触点电接触性能的变化,以 HH52P 电磁继电器为例进行电接触特性参数检测试验,监测了触点动态接触电阻、静态接触电阻、弹跳时间、稳定时间等特性参数,提取与触点动作次数灰色关联度大的参数建立触点电接触特性参数多变量灰色预测模型。利用试验数据分析了多变量灰色模型的预测精度,并与单变量预测模型对比。结果表明,进行灰色关联度分析之后进行建模的多变量灰色模型能够更好地描述触点电接触特性参数变化情况。     

An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method

An accurate and time efficient model of CMOS gate driven coupled-multiple interconnects is presented in this paper for crosstalk induced propagation delay and peak voltage measurements. The proposed model is developed using the finite difference time domain (FDTD) technique for coupled RLC interconnects, whereas the alpha power law model is used to represent the transistors in a CMOS driver. As verified by the HSPICE simulation results, the transient response of the proposed model demonstrates high accuracy. Over the random number of test cases, crosstalk induced peak voltage and propagation delay show average errors of 1.1% and 4.3%, respectively, with respect to HSPICE results.     

A low impedance receiver for power efficient current mode signalling across on-chip global interconnects

In this work we propose a low impedance receiver for on-chip high speed current-mode signalling over global interconnect. The receiver provides a very low input impedance even with a low quiescent power. The low input impedance helps to get high link bandwidth without any passive terminator. Moreover, the receiver has high transimpedance gain over a large bandwidth. This facilitates in reducing the signalling current by 6.7 times compared to a passive termination. A test chip has been fabricated in 0.18 μm CMOS process to test the topology with a prototype global interconnect having a length of 10 mm. Power consumption of the transceiver for a data rate of 2.5 Gbps data is 2 mW. This gives an energy efficiency of 0.8 pJ/b.