A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques

In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second- and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain, -3 dB bandwidth (BW_−3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of +13.1 dBm and +42.8 dBm, respectively. The simulated S₁₁ is less than −11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply.     

采用balun低噪声放大器的5GHz 7.2-dB NF低功耗直接转换接收机前端电路

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm². It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

基于0.25μm GaAs PHEMT工艺的32GHz毫米波单片功率放大器

设计、制造和测试了基于0.25μm栅长GaAs工艺的32GHz毫米波单片功率放大器.该功率放大器采用三级放大,工作电压为6V,工作电流为600mA.带内最大小信号增益为17.4dB,在32GHz具有0.5W的饱和功率输出.     

0.15μmInGaAs PHEMT50MHz-1GHz高线性CATV放大器设计

本文对应用于CATV（有线电视）的50MHz - 1GHz频段的低噪声和高线性度单片微波集成电路（MMIC）放大器进行了设计。设计采用并联电压交流负反馈和源极电流负反馈相结合以扩大带宽和高线性度。本文引入一种新的共源共栅管基极偏置以稳定工作点来进一步提高线性度。该电路由台湾稳懋半导体公司的0.15μm InGaAs PHEMT工艺制作。测试在有线电视频段50MHz-1GHz范围内和75欧姆测试匹配系统中进行。.测试结果表明芯片小信号增益为16.5dB,带内波动小于 1dB。噪声指数在带内为1.7-2.9dB。IIP3高达16dBm。CSO和CTB分别为68dBc和77dBc。芯片面积为0.56 mm2,而功耗在5V供电下为110mA。测试结果表明芯片展现了出色的噪声性能和高线性度,非常适合于有线电视系统。     

应用于802.11a的5.7GHz CMOS LNA设计

使用0.18μm CMOS工艺设计应用于802.11a WLAN的U-NII高频段5.7GHz的LNA.首先选取LNA结构,推导出噪声模型,然后选取在固定功率消耗下最小噪声系数对应的晶体管尺寸,再进行输入输出阻抗匹配和电路调整优化.在使用Bond Wire不加Pad时提供-22.014dB S11,-44.902dB S22,15.063dB S21,-39.44dB S12,2.453dB/2.592dB的噪声系数(NF),-4.1915dBm的三阶互调输入点(IIP3),-15.6dBm的功率1dB压缩点(P1dB)和10mW的功率消耗(Pd).完全考虑Bond Wire和Pad效应的性能参数也已经给出,但噪声系数恶化为3.21/3.23dB,S参数在电路调整优化之后变化不大,整体性能比较突出.     

基于遗传算法的微波低噪声放大器的优化与实现

微波低噪声放大器(LNA)是微波通信系统中接收机的重要器件,其性能直接影响了通信质量的好坏.采用遗传算法这一全局搜索性能较好的数值算法对LNA的增益及噪声进行了优化,根据优化算法设计了2 GHz的微波低噪声放大器,给出了优化设计步骤及实际电路,并对器件进行了测试,可以看出改进后的器件增益增加了3.4 dB,噪声系数降低了0.5,达到了满意的效果.     

双平面掺杂和单平面掺杂PHEMT器件的性能比较

研制了Al0 .2 4 Ga0 .76 As/ In0 .2 2 Ga0 .78As单平面掺杂PHEMT器件(SH - PHEMT)和双平面掺杂PHEMT器件(DH- PHEMT) ,并对其特性进行了比较.由于采用了双异质结、双平面掺杂的设计,DH- PHEMT能将载流子更好地限制在沟道中,得到更大的二维电子气浓度和更均匀的二维电子气分布,这些都有利于提高器件的性能.因此,DH- PHEMT器件具有更好的线性度,在较大的栅压范围内具有高的跨导和更大的电流驱动能力.这说明DH-PHEMT器件更加适用于高线性度应用的微波功率器件.     

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with g_m boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.     

一个应用于卫星导航接收机的低功耗可配置双频多模射频前端

本文给出了一个应用于GPS、北斗、伽利略和Glonass四种卫星导航接收机的高性能双频多模射频前端。该射频前端主要包括有可配置的低噪声放大器、宽带有源单转双电路、高线性度的混频器和带隙基准电路。详细分析了寄生电容对源极电感负反馈低噪声放大器输入匹配的影响,通过在输入端使用两个不同的LC匹配网络和输出端使用开关电容的方法使低噪声放大器可以工作在1.2GHz和1.5GHz频带。同时使用混联的有源单转双电路在较大的带宽下仍能获得较好的平衡度。另外,混频器采用MGTR技术在低功耗的条件下来获得较高的线性度,并不恶化电路的其他性能。测试结果表明：在1227.6MHz和1557.42MHz频率下,噪声系数分别为2.1dB和2.0dB,增益分别为33.9dB和33.8dB,输入1dB压缩点分别0dBm和1dBm,在1.8V电源电压下功耗为16mW。     

220GHz低噪声放大器研究

基于IHP锗硅BiCMOS工艺,研究和实现了两种220 GHz低噪声放大器电路,并将其应用于220 GHz太赫兹无线高速通信收发机电路。一种是220 GHz四级单端共基极低噪声放大电路,每级电路采用了共基极（Common Base, CB）电路结构,利用传输线和金属-绝缘体-金属(Metal-Insulator-Metal, MIM)电容等无源电路元器件构成输入、输出和级间匹配网络。该低噪放电源的电压为1.8 V,功耗为25 mW,在220 GHz频点处实现了16 dB的增益,3 dB带宽达到了27 GHz。另一种是220 GHz四级共射共基差分低噪声放大电路,每级都采用共射共基的电路结构,放大器利用微带传输线和MIM电容构成每级的负载、Marchand-Balun、输入、输出和级间匹配网络等。该低噪放电源的电压为3 V,功耗为234 mW,在224 GHz频点实现了22 dB的增益,3 dB带宽超过6 GHz。这两个低噪声放大器可应用于220 GHz太赫兹无线高速通信收发机电路。