Fast and scalable parallel layout decomposition in double patterning lithography

For 32/22 nm technology nodes and below, double patterning (DP) lithography has become the most promising interim solutions due to the delay in the deployment of next generation lithography (e.g., EUV). DP requires the partitioning of the layout patterns into two different masks, a procedure called layout decomposition. Layout decomposition is a key computational step that is necessary for double patterning technology. Existing works on layout decomposition are all single-threaded, which is not scalable in runtime and/or memory for large industrial layouts. This paper presents the first window-based parallel layout decomposition methods for improving both runtime and memory consumption. Experimental results are promising and show the presented parallel layout decomposition methods obtain upto 21× speedup in runtime and upto 7.5×reduction in peak memory consumption with acceptable solution quality.     

Synchronization controller for a 3-R planar parallel pneumatic artificial muscle (PAM) robot using modified ANFIS algorithm

Parallel manipulator is a closed-kinematic chain mechanism in which performance of its end effector – moving platform is contributed by its independent actuators. In traditional designs, each elemental actuator has its own controller as well as reference input, and it works independently without gathering information from its neighbors. Consequently, as one of the actuators cannot keep up with the others, the platform performance is easily deteriorated due to the lack of coherence between these actuators. Therefore, the aim of this paper is to design a 3-R planar parallel robot and develop a proper synchronization controller for its tracking control task. Adaptive Network Based Fuzzy Inference System (ANFIS) algorithm was modified and applied as the main strategy of this synchronization controller. The controller is then able to compensate errors between the actuators and enforce them to cooperate harmonically with each other regardless external disturbances caused by the outside environment or geometrical constraints of the closed-loop structure. Simulations and practical experiments on a scaled parallel robot were carried out to evaluate the designed controller. The results showed that by applying the proposed control technique, the working errors of the component actuators converged quickly to zero almost at the same time. As a result, the tracking performance of the common platform was significantly improved in comparison with the performance when applying a non-synchronization controller. The proposed method is effective in controlling systems which require collaborations between the sub-agents.     

高斯滤波调制解调器的实现技术

无线数据传输是人们普遍使用的一种通信手段,基于DSP的数字调制解调技术的研究也得到人们的高度重视。根据无线数据传输的特点,将高斯滤波的技术运用于MSK调制技术,设计了一种适合无线数据传输的GMSK调制解调器,给出了实现原理、系统框图和软件控制流程图。实际测试表明,该调制解调器提高了数字移动通信的频谱利用率和通信质量,调制后的中频信号对邻道辐射小于60 dB,符合无线通信的要求,可广泛应用于无线数传设备。     

多分辨率融合输入的U型视网膜血管分割算法

针对视网膜血管拓扑结构不规则、形态复杂和尺度变化多样的特点,该文提出一种多分辨率融合输入的U型网络(MFIU-Net),旨在实现视网膜血管精准分割。设计以多分辨率融合输入为主干的粗略分割网络,生成高分辨率特征。采用改进的ResNeSt代替传统卷积,优化血管分割边界特征;将并行空间激活模块嵌入其中,捕获更多的语义和空间信息。构架另一U型精细分割网络,提高模型的微观表示和识别能力。一是底层采用多尺度密集特征金字塔模块提取血管的多尺度特征信息。二是利用特征自适应模块增强粗、细网络之间的特征融合,抑制不相关的背景噪声。三是设计面向细节的双重损失函数融合,以引导网络专注于学习特征。在眼底数据用于血管提取的数字视网膜图像(DRIVE)、视网膜结构分析(STARE)和儿童心脏与健康研究(CHASE_DB1)上进行实验,其准确率分别为97.00%, 97.47%和97.48%,灵敏度分别为82.73%, 82.86%和83.24%,曲线下的面积(AUC)值分别为98.74%, 98.90%和98.93%。其模型整体性能优于现有算法。     

A memory efficient parallel layered QC-LDPC decoder for CMMB systems

This paper presents a memory efficient architecture of layered decoder for the dual-rate LDPC codes in the China Multimedia Mobile Broadcasting (CMMB) system. An efficient scheme for reducing the memory block number is proposed to increase the memory usage efficiency, so that the quantity of memory bits, decoder area and power consumption is significantly reduced. At the same time, the memory structure keeps the “one cycle one layer access” timing schedule to achieve high decoding throughput. Furthermore, the early termination strategy is employed to further increase the throughput; a non-uniform quantization scheme and an area efficient calculation module are developed to further improve the memory efficiency and hardware resource efficiency, respectively. By using SMIC 130 nm 1P7M CMOS process, the decoder is implemented and the core area is 5.29 mm². The total memory bits consumption is only 130.5 K which consumes 2.53 mm² memory area.     

LS SIMD计算机的并行技术

文章主要讨论了LSSIMD计算机中所采用的并行技术数据并行技术、三级指令流水线并行技术与三组指令并行执行技术。     

亚微米并行激光直写系统的建模及仿真研究

提出了一种基于强度调制型空间光调制器（SLM）的并行激光直写系统，建立了该系统的数学模型，并以闪耀光栅的制作为例，给出了该并行激光直写系统的仿真分析结果。研究表明，该系统可实现的最小特征尺寸达到亚μm级，采用逐个图形进行曝光的方式使其具有内在的并行特性，可大大提高激光直写的速度；该系统所制作的二元光学器件类似连续轮廓器件，理论上可达到80%以上的衍射效率。     

基于F型管壳的旋转缝焊技术研究

本文深入研究了旋转缝焊技术,讨论了缝焊中焊边受力、速度变化和热量分布情况,分析了影响旋转缝焊气密性的主要因素.     

A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards

Huffman coding is a popular and important lossless compression scheme for various multimedia applications. This paper presents a low-latency parallel Huffman decoding technique with efficient memory usage for multimedia standards. First, the multi-layer prefix grouping technique is proposed for sub-group partition. It exploits the prefix characteristic in Huffman codewords to solve the problem of table size explosion. Second, a two-level table lookup approach is introduced which can promptly branch to the correct sub-group by level-1 table lookup and decode the symbols by level-2 table lookup. Third, two optimization approaches are developed; one is to reduce the branch cycles and the other is parallel processing between two-level table lookup and direct table lookup approaches to fully utilize the advantage of VLIW parallel processing. An AAC Huffman decoding example is realized on the Parallel Architecture Core DSP (PAC DSP) processor. The simulation results show that the proposed method can further improve about 89% of decoding cycles and 33% of table size comparing to the linear search method.

PHEV驱动系统结构分析与仿真研究

对插电式混合动力汽车(PHEV)的串、并联驱动系统结构进行分析.以中型SUV为例,确定了整车动力系统参数和控制策略;使用Advisor进行仿真.仿真结果表明:在控制策略和工况既定的前提下,当所用电池容量较小时,并联PHEV总体性能优于串联PHEV;电池容量增加后,串联PHEV表现出良好的适应性.