同步数字体系中155Mbit/s净荷的误码测试

本文基于光纤传输同步数字体系(S D H)系统的开发背景,较为详细地总结了155Mbit/s速率下的净荷误码测试机理.最后给出了净荷的误码测试方法以及误码测试系统的信号流程.     

基于广电SDH网的信号覆盖与新闻回传系统

如何建设咸宁电视台公共频道下传及各县（市）的新闻上传通道就成为一个需要解决的问题，本文对建立内部专用以太网、专用光纤点对点方式以及视音频数据复用三种方案进行了比较和论证，最终选择了视音频数据复用方案，较好地解决了咸宁电视台两个频道的下传和各县（市）的新闻上传问题。     

SDH传输网子网管理系统及其应用研究

本文是针对2488—01B型SDH传输设备，详细介绍了SDH传输网子网管理系统的结构与类型特点，并且在此设备的基础上，介绍了SDH传输网子网管理系统的具体应用。     

传输系统光功率自动采集方案及系统实现

创新性地提出了传输网络光功率自动采集系统,较详细地阐述了该系统的功能结构、数据库设计、采集步骤、数据呈现及应用前后的效益对比,并通过案例进一步阐述了该系统的具体应用。     

城域光网建设的若干技术分析

阐述目前国内常见的建设城域网的技术并深入分析比较几种技术的优势和劣势 ,并就CWDM技术的发展和应用方案实例作了简要描述     

光传输网络中的链路保护与业务保护之间的关系

介绍了用悬链线公式代替抛物线公式计算架空通信导线垂度的方法,并以软件的方式实现了复杂条件下的自动计算。     

IP技术在未来广电节目传输组网中的应用前景展望

本文介绍了基于IP技术的“TS over IP”、“IP组网”和“IP over SDH”等关键技术的应用情况,并描绘了未来基于IP技术的广电节目传输网的设计模型,对未来广电节目传输网的发展前景进行了展望.     

VLSI Implementation of Forward Error Control Technique for ATM Networks

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.     

Fault tolerance in Clos–Knockout multicast ATM switch

In this paper, we propose a new architecture for multicast ATM switches with fault tolerant capability based on the Clos–Knockout switch. In the new architecture, each stage has one more redundant switch module. If one switch module is faulty, the redundant module would replace the faulty one. On the other hand, under the fault‐free condition, the redundant modules in the second and third stages will provide additional alternative internal paths, and hence improve the performance. The performance analysis shows that the cell loss probability is lower than the original architecture when all modules are fault free, and the reliability of the original architecture is improved. Copyright © 2002 John Wiley & Sons, Ltd.     

基于FPGA的数字交叉连接矩阵的设计

采用两级结构设计了一种4×4SDXC矩阵,用以实现四路不同STM-1输入信号的完全无阻塞交叉连接。整个设计采用FPGA设计方法,阐述了SDH数字交叉连接矩阵的交换实质,重点解析了空分交换单元和时分交换单元的结构框图。最后,采用Quartus Ⅱ软件进行功能仿真,验证了设计的正确性。