MOSFET单粒子翻转效应的二维数值模拟

用MEDICI二维模拟软件对MOSFET的单粒子翻转现象进行了计算，力图从理论上建立分析器件单粒子翻转的可靠手段，通过输入不同粒子的线性能量传输值，得到了某一结构器件的翻转概率与线性能量传输值的关系曲线，分析了不同结构参数的变化对单粒子翻转的影响，模拟得到的结果与电荷漏斗模型相吻合，表明所建立的物理模型的正确性。     

外包钢加固法及其软件设计--梁加固(湿式)

针对目前加固行业外包型钢加固法应用日益广泛的现状 ,依据《混凝土结构加固技术规程》(CECS 2 5∶90 ) ,阐述了钢筋混凝土梁受弯加固的基本计算理论。介绍了东大迪普加固软件系统的外包钢受弯加固模块编制方法。最后 ,通过应用实例进行详细说明     

近地卫星长期SEU事件退火分析

针对近地卫星在轨运行中的单粒子翻转事件(Single Event Upset,SEU)的退火问题,选取某卫星器件长期积累的SEU数据为样本,在分析器件长期温度变化的基础上,详细统计SEU事件的星下点以及年、月等时空分布特征,并讨论SEU事件与地球磁场分布、F10.7曲线、中子监测数据的关联特性,最后以SEU事件发生的平均间隔为目标,建立退火模型,用实际数据进行退火估计。结果表明,SEU事件星下点发生在南大西洋异常区的达到67%以上,发生在南、北两极高纬度区域的超过16%,其它区域的不足17%;8、9、10、12这4个月份的SEU事件最多,占全年的38%以上;以远、近日点为参考时,发生在4～9月的约占50%,发生在其它月份的也在50%附近,两者十分接近;长期SEU事件受宇宙射线、太阳活动影响明显,长期性变化以宇宙射线影响为主,短期性变化以太阳活动影响为主;在轨道周期内温度变化约2℃、长期温升接近5℃的条件下,SEU事件时间间隔的均值约4.57d,退火零值约1.56×10-13 d,退火因子约7.94×10-15 d-1,衰减零值约24.34d,衰减因子约0.12d-1,退火特征并不明显,退火影响可不用考虑。     

40 nm CMOS工艺下的低功耗容软错误锁存器

为了降低集成电路的软错误率,该文基于时间冗余的方法提出一种低功耗容忍软错误锁存器。该锁存器不但可以过滤上游组合逻辑传播过来的SET脉冲,而且对SEU完全免疫。其输出节点不会因为高能粒子轰击而进入高阻态,所以该锁存器能够适用于门控时钟电路。SPICE仿真结果表明,与同类的加固锁存器相比,该文结构仅仅增加13.4%的平均延时,使得可以过滤的SET脉冲宽度平均增加了44.3%,并且功耗平均降低了48.5%,功耗延时积(PDP)平均降低了46.0%,晶体管数目平均减少了9.1%。     

基于DSP的实时目标特征提取算法

在空间环境中,长时间运行的空间飞行器信息处理系统存储器容易发生单粒子翻转现象(SEU),而单粒子翻转现象是导致空间飞行器失效的主要原因之一。基于此,通过分析SEU现象对不同类型存储器的影响,阐述SEU现象对加载可靠性的影响。通过重新设计加载系统结构,并引入三模冗余、检纠错编码和定时刷新FLASH存储器的方法,降低系统加载时由于SEU而失败的概率,提高系统加载运行的可靠性。     

Differential cross sections on fragment (2 ≤ Z ≤ 9) production for carbon,aluminum and silicon induced by tens-of-MeV protons

The double-differential cross sections (DDXs) for the inclusive reactions producing heavy nuclei with Z = 2–9 (fragments) from carbon, aluminum, and silicon targets induced by 50 and 70 MeV protons are systematically measured at several angles (30°, 60°, 90°, and 135°) using a specially developed Bragg curve counter and the energy-time-of-flight method. The DDXs of a silicon target for the proton-induced reaction producing fragments heavier than lithium were measured for the first time. The present results are compared with past experimental data, the LA150 evaluated data by the Los Alamos group and several intranuclear cascade models (Bertini and ISOBAR), and the JAEA-version quantum molecular dynamics model (JQMD) coupled with the Generalized Evaporation Model (GEM), which are implemented in the Particle and Heavy Ion Transport code System (PHITS). The present results agree well with the past experimental data and LA150 data for α -particle production. For the fragments heavier than lithium, the present results show forward-peak angular distributions rather than isotropic ones stored in LA150. Calculations with the ISOBAR and GEM models well reproduced our experimental results except for light fragments especially in the high-energy region.     

On-Line Testing for VLSI—A Compendium of Approaches

This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST, or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test,...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.     

Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk com-plementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm2).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm2),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm2)owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm2)),the benefit of the EDAC code is reduced significantly because the multi-bit upset pro-portion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distri-butions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some sug-gestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.     

SEU的二维数值模拟

本文阐述了单粒子效应原理和损伤机理,对MEDICI软件进行了简要介绍。运用MEDICI软件分别对体硅和SOI(Silicon-On-Insulator)衬底材料进行CMOS SRAM的SEU(Single -Event Upset)模拟实验,得出实验结果,并对实验结果进行分析,证明了SOI材料有良好的抗辐射加固特性,体现出SOI材料的优越性。     

A compact AES core with on-line error-detection for FPGA applications with modest hardware resources

This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity codes. The parity prediction is implemented in the AES encryption, decryption, and key expansion process. The developed solution has been upgraded to an efficient BIST with a high fault coverage and a low hardware overhead.