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排序方式: 共有127条查询结果,搜索用时 15 毫秒
111.
针对民用机载电子硬件的现场可编程门阵列(FPGA)芯片高使用频率和长时间运行的特点,以及联邦航空管理局(FAA)等提出的审查条例对单粒子翻转效应(SEU)的防护要求,介绍了民用机载电子硬件的SEU效应评估研究的必要性。并且从民用机载电子硬件主流的三模冗余容错电路入手,设计了SEU效应仿真测试电路。将冗余系统与多时钟沿触发相结合,提高了系统的检错能力。对冗余系统进行仿真SEU故障注入,通过与参照单元的比较,可对SEU效应引起的失效的发生进行仿真测试。 相似文献
112.
FPGA器件在航天领域应用广泛,然而在空间环境下,基于SRAM工艺的FPGA器件极易受到单粒子翻转(Single Event Upsets,SEU)影响而导致电路发生软错误。针对具有代表性的Xilinx Virtex系列器件进行了SEU评估方法的研究,设计并开发了一款面向Virtex器件的SEU效应评估工具,并与FPGA标准设计流程进行了有效融合。实验结果表明,提出的评估方法和工具对Virtex器件的SEU效应可以进行准确的评估,从而为FPGA结构设计和应用开发提供先于硬件实现的软件验证环境,对高可靠性FPGA芯片的研究、开发和设计都具有重要意义。 相似文献
113.
《Microelectronics Reliability》2015,55(6):863-872
As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when particles strike on any one of its single node. Furthermore, it can efficiently mask the input single event transient (SET). A set of HSPICE post-layout simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures, and the comparison results among the latches of type 4 show that the proposed latch reduces at least 39% power consumption and 67.6% power delay product. Moreover, the proposed latch has a second lowest area overhead and a comparable ability of the single event multiple upsets (SEMUs) tolerance among the latches of type 4. Finally, the impacts of process, supply voltage and temperature variations on our proposed latch and previous latches are investigated. 相似文献
114.
On-Line Testing for VLSI—A Compendium of Approaches 总被引:1,自引:1,他引:0
This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST, or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test,...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensive fabrication process such as SOI, etc. 相似文献
115.
116.
《Microelectronics Reliability》2015,55(6):990-1004
Fault security indicates ability to provide error detection or fetch correct output. Fault security assures possibility of using either hardware redundancy or time redundancy to optimize the overheads associated with fault security. However, generation (design space exploration (DSE)) of an optimal fault secured datapath structure based on user power–delay budget during high level synthesis (HLS) in the context k-cycle transient fault is considered an intractable problem. This is due to the fact that for every type of candidate design solution produced during exploration, a feasible k-cycle fault secured datapath may not exist which satisfies the conflicting user constraints/budget. Secondly, insertion of inapt cut (resulting in an additional checkpoint) to optimize delay overhead associated with fault security in most cases may not result in optimal solutions in the context of user constraints/budgets. The solutions to the above problems have not been addressed in the literature so far. The paper therefore presents the following novelties: (a) an algorithm for fault secured DSE process (b) handling k-cycle transient faults during DSE (c) schemes for selecting appropriate edges for inserting cuts that selects available locations in the scheduled Control Data Flow Graph (CDFG) which minimizes delay overhead associated with fault security (d) swarm intelligence (particle swarm optimization) driven DSE process that adaptively/intelligently computes the candidate design solutions for generating an optimal fault secured datapath.Results of the proposed approach when tested on standard benchmarks yielded optimal results in most cases as evident from the data obtained for generational distance (GD), spacing (S), spreading (Δ) and weighted metric (Wm). Further, results of comparison with a recent approaches indicated significant reduction of final cost (better quality) for the proposed approach. 相似文献
117.
在空间中,辐射粒子入射半导体器件,会在器件中淀积电荷.这些电荷被器件的敏感区域收集,造成存储器件(如静态随机存储器(SRAM))逻辑状态发生变化,产生单粒子翻转(SEU)效应.蒙特卡洛工具-Geant4能够针对上述物理过程进行计算机数值模拟,可以用于抗辐射器件的性能评估与优化.几何描述标示语言(GDML)能够在Geant4环境下对器件模型进行描述.通过使用GDML建立三维的器件结构模型,并使用Geant4进行不同能量质子入射三维器件模型的仿真.实验结果表明,在三维器件仿真中低能质子要比高能质子更容易引起器件的单粒子翻转效应. 相似文献
118.
119.
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources
Uroš LegatAuthor Vitae Anton Biasizzo Author VitaeFranc Novak Author Vitae 《Microprocessors and Microsystems》2011,35(4):405-416
This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity codes. The parity prediction is implemented in the AES encryption, decryption, and key expansion process. The developed solution has been upgraded to an efficient BIST with a high fault coverage and a low hardware overhead. 相似文献
120.