SOI光波导和集成波导光开关矩阵

报道了基于SOI (silicon-on-insulator）材料的光波导和集成波导光开关矩阵的最新研究进展. 给出了截面为梯形的脊波导的单模条件，设计制备了MMI (multimode interference）集成耦合器和基于Mach-Zehnder光波导干涉仪的热光型2×2光开关，开关转换速度达到了5～8μs，驱动功耗仅为140mW，是当前国际上同类型光开关中转换速度最快的. 在此基础上制备成功了4×4波导光开关矩阵，并实现了光信号在不同信道间的转换.     

Ultra-high temperature (>300 °C) suspended thermodiode in SOI CMOS technology

This paper reports for the first time on the performance and long-term stability of a silicon on insulator (SOI) thermodiode with tungsten metallization, suspended on a dielectric membrane, at temperatures beyond 300 °C. The thermodiode has been designed and fabricated with minute saturation currents (due to both small size and the use of SOI technology) to allow an ultra-high temperature range and minimal non-linearity. It was found that the thermodiode forward voltage drop versus temperature plot remains linear up to 500 °C, with a non-linearity error of less than 7%. Extensive experimental results on performance of the thermodiode that was fabricated using a Complementary Metal Oxide Semiconductor (CMOS) SOI process are presented. These results are backed up by infrared measurements and a range of 2-D (dimension) and 3-D simulations using ISE and ANSYS software. The on-chip drive electronics for the thermodiode and the micro-heater, as well as the sensor transducing circuit were placed adjacent to the membrane. We demonstrate that the thermodiode is considerably more reliable in long-term direct current operation at high temperatures when compared to the more classical resistive temperature detectors (RTDs) using CMOS metallization layers (tungsten or aluminum). We also compare a membrane thermodiode with a reference thermodiode placed on the silicon substrate and assess their relative performance at elevated temperatures. The experimental results from this comparison confirm that the thermodiode suffers minimal piezo-junction/piezo-resistive effects.     

Two-dimensional threshold voltage analytical modes of DMG strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further,the threshold voltage model correctly predicts a "rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.     

The Bipolar Field-Effect Transistor: ⅩⅢ. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These ex-amples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impure-thin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concen-tration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.     

深亚微米SOI工艺SoC设计中天线效应的消除

深亚微米SOI片上系统芯片(SoC)因其工艺特性,按照常规的布局布线(PNR)流程,出现了约一万个天线效应违规。介绍了一种在布局布线阶段不插入反偏二极管就可以消除大量天线效应违规的优化迭代流程。通过对天线效应的产生以及天线比率公式的分析,从线长和栅面积角度考虑天线效应的修复,结合自动布局布线设计工具SoC Encounter对这些因素的控制,可以在布局布线阶段消除天线效应的违规,并能与版图验证的结果保持一致。在一款通用抗辐照SoC芯片的设计中,应用该优化流程在布局布线阶段消除了设计中的天线效应违规,有效节约了芯片整体设计时间。     

SOINMOSFET的双峰及辐射效应研究

通过对SOINMOFET的总剂量辐照试验,对器件辐照中的双峰效应进行研究。文中给出了双峰效应的表征。试验结果表明双峰的形状随辐照总剂量的增加而改变,并分析了具体的原因。另外,背栅晶体管对主要晶体管的耦合效应要远远大于其对寄生晶体管的作用。     

用于智能功率集成电路的PTG-LDMOST

提出一种用于智能功率集成电路的基于绝缘体上硅(SOI)的部分槽栅横向双扩散MOS晶体管(PTG-LDMOST)。PTG-LDMOST由传统的平面沟道变为垂直沟道,提高了器件击穿电压与导通电阻之间的折衷。垂直沟道将开态电流由器件的表面引向体内降低了导通电阻,而且关态的时候耗尽的JFET区参与耐压,提高单位漂移区长度击穿电压。仿真结果表明:对于相同的10微米漂移区长度,新结构的击穿电压从常规结构的111V增大到192V,增长率为73%。     

Numerical Analysis of Characterized Back Interface Traps of SOI Devices by R-G Current

Characterized back interface traps of SOI devices by the Recombination-Generation (R-G) curren: has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSiS-ISE. The basis of the principle for the R-G current's characterizing the back interface traps of SOI lateral p+p-n+ diode has been demonstrated. The dependence of R-G cur rent on interface trap characteristics has been examined, such as the state density, surface recombination velocity and the trap energy level. The R-G current proves to be an effective tool for monitoring the back interface of SOI devices.     

利用改善的体连接技术制备SOI LDMOSFET

对功率器件中常用的体连接技术进行了改进,利用一次硼离子注入技术形成体连接.采用与常规1μm SOI(硅-绝缘体)CMOS工艺兼容的工艺流程,在SIMOX SOI片上制备了LDMOS结构的功率器件.器件的输出特性曲线在饱和区平滑,未呈现翘曲现象,说明形成的体连接有效地抑制了部分耗尽器件的浮体效应.当漂移区长度为2μm时,开态击穿电压达到10V,最大跨导17.5mS/mm.当漏偏压为5V时,SOI器件的泄漏电流数量级为1nA,而相应体硅结构器件的泄漏电流为1000nA.电学性能表明,这种改善的体连接技术能制备出高性能的SOI功率器件.     

硅膜厚度对0.1μm SOI槽栅NMOS器件特性的影响

SOI技术和槽栅MOS新器件结构是在改善器件特性方面的两大突破,SOI槽栅MOS器件结构能够弥补体硅槽栅MOS器件在驱动能力和亚阈值特性方面的不足,同时也保证了在深亚微米领域的抑制短沟道效应和抗热载流子效应的能力.仿真结果显示硅膜厚度对SOI槽栅MOS器件的阈值电压、亚阈值特性和饱和驱动能力都有较大影响,选择最佳的硅膜厚度是获得较好的器件特性的重要因素.