Layer-transfer process for silicon-on-insulator with improved manufacturability

We observe hydrogen platelet buildup in single-crystalline silicon caused by hydrogen-plasma processing. The platelets are aligned along a layer of lattice defects formed in silicon before the plasma processing. The buried-defect layer is formed by either silicon-into-silicon or argon-into-silicon implantation. We discuss the platelet nucleation, growth, and merge phenomena and discuss applicability of the plasma hydrogenation to silicon-on-insulator (SOI) wafer fabrication by layer transfer.     

Ultra-high temperature (>300 °C) suspended thermodiode in SOI CMOS technology

This paper reports for the first time on the performance and long-term stability of a silicon on insulator (SOI) thermodiode with tungsten metallization, suspended on a dielectric membrane, at temperatures beyond 300 °C. The thermodiode has been designed and fabricated with minute saturation currents (due to both small size and the use of SOI technology) to allow an ultra-high temperature range and minimal non-linearity. It was found that the thermodiode forward voltage drop versus temperature plot remains linear up to 500 °C, with a non-linearity error of less than 7%. Extensive experimental results on performance of the thermodiode that was fabricated using a Complementary Metal Oxide Semiconductor (CMOS) SOI process are presented. These results are backed up by infrared measurements and a range of 2-D (dimension) and 3-D simulations using ISE and ANSYS software. The on-chip drive electronics for the thermodiode and the micro-heater, as well as the sensor transducing circuit were placed adjacent to the membrane. We demonstrate that the thermodiode is considerably more reliable in long-term direct current operation at high temperatures when compared to the more classical resistive temperature detectors (RTDs) using CMOS metallization layers (tungsten or aluminum). We also compare a membrane thermodiode with a reference thermodiode placed on the silicon substrate and assess their relative performance at elevated temperatures. The experimental results from this comparison confirm that the thermodiode suffers minimal piezo-junction/piezo-resistive effects.     

Two-dimensional threshold voltage analytical modes of DMG strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further,the threshold voltage model correctly predicts a "rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.     

液晶非线性光学和应用

描述了液晶非线性光学原理，介绍了液晶非线性光学元件的结构和制作方法，报道了我们的最新实验结果，提出了液晶非线性光学的研究方向和应用领域。     

双栅MOSFET的研究与发展

具有特殊结构的双栅ＭＯＳＦＥＴ是一种高速度、低功耗ＭＯＳＦＥＴ器件,符合未来集成电路发展的方向。文章介绍了多种双栅ＭＯＳＦＥＴ的结构、优点,以及近年来国内外对双栅ＭＯＳＦＥＴ的研究成果。     

注入条件对SIMOX材料的影响

利用ＲＢＳ和ＴＥＭ技术分析研究了不同注入剂量、注入方式（单重注入，多重注入）对ＳＩＭＯＸ材料各层结构的影响，特别着重研究了Ｓｉ／ＳｉＯ２界面过渡区受注入条件的影响。结果表明，在注入剂量相同的情况下，多重注入不仅能改善顶层单晶、ＳｉＯ２绝缘层的质量，而且能显著减小Ｓｉ／ＳｉＯ２界面过渡区宽度。     

CMOS／SOI电路模拟与参数提取

ＳＯＩ－ＭＯＳＦＥＴ主要模型参数得一致的提取，因而该模型嵌入ＳＰＩＣＥ后能保证ＣＭＯＳ／ＳＯＩ电路的正确模拟工作，从ＣＭＯＳ／ＳＯＩ器件和环振电路的模拟结果和实验结果看，两者符合得较好，说明我们所采用的ＳＯＩ ＭＯＳＦＥＴ器件模型及其参数提取都是成功的。     

The Bipolar Field-Effect Transistor: ⅩⅢ. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These ex-amples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impure-thin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concen-tration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.     

SOI抗总剂量辐射加固工艺栅氧可靠性研究

文章对采用了埋层二氧化硅抗总剂量加固工艺技术的SOI器件栅氧可靠性进行研究,比较了干法氧化和湿法氧化工艺的栅氧击穿电荷,干法氧化的栅氧质量劣于湿法氧化。采用更敏感的12.5nm干法氧化栅氧工艺条件,对比采用抗总剂量辐射加固工艺前后的栅氧可靠性。抗总剂量辐射加固工艺降低了栅氧的击穿电压和击穿时间。最后通过恒压法表征加固工艺的栅氧介质随时间击穿(TDDB)的可靠性,结果显示抗总剂量辐射加固工艺的12.5nm栅氧在常温5.5V工作电压下TDDB寿命远大于10年,满足SOI抗总剂量辐射加固工艺对栅氧可靠性的需求。     

SOI数模混合集成电路的串扰特性分析

采用二维TMA Medici模拟软件对SOI结构的串扰特性进行了分析.模拟发现随着频率的增加,SOI的埋氧化物对串扰噪声几乎不起隔离作用,同时,连接SOI结构的背衬底可以在很大程度上减小串扰的影响.还对减少串扰的沟槽隔离工艺、保护环及差分结构的有效性进行了比较分析,对一些外部寄生参数对串扰的影响也进行了研究.并给出了SOI结构厚膜和薄膜结构体掺杂浓度对噪声耦合的影响,所得到的结果对设计低噪声耦合的SOI数模混合集成电路具有指导性的作用.