4H-SiC肖特基微型同位素电池(英文)

半导体同位素电池由于其寿命长、集成性优良、环境适应性强等特点成为解决MEMS能源问题的理想手段。利用4H-SiC材料的宽禁带特性,制造了4H-SiC肖特基同位素电池。对电池的耗尽层厚度以及掺杂浓度进行了优化设计,对肖特基金属进行了选择。使用4mCi/cm2的63Ni作为同位素电池的放射源对制造的同位素电池进行了测试。测试结果表明,该同位素电池可以获得31.3nW/cm2的功率密度、0.5V的开路电压、3.13×10-8A/cm2的短路电流密度和1.3%的转换效率。将电池的输出特性和硅基的平板型、3D结构电池输出特性进行了比较,证明4H-SiC肖特基同位素电池能够获得较高的功率密度。电池的性能可通过提升势垒高度、提高工艺质量、更换同位素等方式得到提高。     

Current–voltage characteristics of AlCdO Schottky contact on the polished and unpolished p-type Si surfaces with and without light illumination

In this study, the current-voltage characteristics of the AlCdO/unpolished p-type Si and AlCdO/polished p-type Si Schottky diodes with and without light illumination were examined. It is found that the Schottky barrier height (the series resistance) of the AlCdO/unpolished p-type Si Schottky diode is higher (lower) than that of the AlCdO/polished p-type Si Schottky diode. The power conversion efficiency of the AlCdO/p-type Si devices in the light (AM 1.5 G, 100 mW/cm²) was improved by increasing built-in potential at the AlCdO/p-type Si interfaces and reducing the device series resistance and surface reflectivity. It is shown that the device surface roughness plays an essential role in improving the device performance.     

Comparison of PVD, PECVD & PEALD Ru(-C) films as Cu diffusion barriers by means of bias temperature stress measurements

The diffusion barrier properties of PVD Ru and PECVD / PEALD Ru-C films, deposited by RuEtcp₂ precursor and N₂/H₂ plasma, were compared on the basis of bias temperature stress measurements. An MIS test structure was used to distinguish between thermal diffusion induced by annealing and a Cu field drift due to applied electric fields. BTS-CV, TZDB and TDDB measurements revealed that the barrier performance is significantly better for PEALD and PECVD Ru-C films. This improvement is associated with carbon impurities in the Ru films with a concentration in the order of several percent according to ToF-SIMS and ERDA. The TDDB mean time to failure at 250 °C, +5 MV/cm was 7 s for PVD Ru samples, ≈500 s for PECVD Ru-C, ≈800 s for PEALD Ru-C and >3600 s for PVD TaN. Triangular voltage sweep measurements at 300 °C, 0.1 V/s confirmed the presence of Cu ions inside the SiO₂ for degraded dots, in contrast to the Al reference sample and to PVD TaN, which performed best among all the Cu barriers under test. XRD data suggests that PEALD and PECVD Ru-C films are only weakly crystalline.     

以系统的理念,有效防治建筑裂渗病害

分析了导致建筑渗、漏、裂质量问题的主要原因;指出建筑渗、漏、裂问题很大程度上与业界过于依赖以物理屏障将水隔绝或封堵的技术理念有很大关系;提出要以系统的理念处理好建筑的渗、漏、裂质量问题.     

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported,to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions.This novel structure offers low barrier height at the source and offers high ON-state current.The ION/IoFF of ISE-CGAA-SB-MOS-FET increases by 1177 times and offers steeper subthreshold slope (～60 mV/decade).However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate,dual metal gate,single metal gate with ISE,and dual metal gate with ISE has been presented.The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design.The numerical simulation is performed using the ATLAS-3D device simulator.     

CeO_2掺杂引起SnO_2压敏电阻的晶粒尺寸效应

研究了掺CeO2对SnO2Co2O3Ta2O5压敏电阻器性能的影响。研究发现:随着x(CeO2)从0增加到1%,压敏电压从190 V/mm增加到205 V/mm,相对介电常数从3 317减小到2 243,晶粒平均尺寸从12.16 mm减小到6.23 mm,在晶界上的Ce4+阻碍了SnO2晶粒的生长。为了解释样品电学非线性性质的起源,笔者提出了SnO2Co2O3Ta2O5CeO2晶界缺陷势垒模型。同时,对该压敏电阻器进行了等效电路分析,试验测量与等效电路分析结果相符。     

6H-SiC Schottky二极管的正向特性

提出了一种考虑Schottky结势垒不均匀性和界面层作用的Si C Schottky二极管( SBD)正向特性模型,势垒的不均匀性来自于Si C外延层上的各种缺陷,而界面层上的压降会使正向Schottky结的有效势垒增高.该模型能够对不同温度下Si C Schottky结正向特性很好地进行模拟,模拟结果和测量数据相符.它更适用于考虑器件温度变化的场合,从机理上说明了理想因子、有效势垒和温度的关系.     

Fabrication of Schottky barrier MOSFETs using self-assembly CoSi2 nanopatterning and spacer gate technologies

A self-assembly patterning method for generation of epitaxial CoSi₂ nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n⁺-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO₂ and 300 nm Si₃N₄. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi₂ layer and a subsequent out-diffusion process to form the n⁺-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated.     

Pinhole density measurements of barriers deposited on low-k films

Evaluation of diffusion barrier integrity is an important issue in advanced interconnects. A diffusion barrier separating Cu from low-k must be as thin as possible and must not contain pinholes. We have developed a method for measuring pinhole density in diffusion barriers deposited on low-k materials. The method employs ellipsometric porosimetry for measuring diffusion of toluene in a porous low-k film beneath the barrier in question.     

Enhanced thermal stability of a sputtered titanium-nitride film as a diffusion barrier for capacitor-bottom electrodes

The effect of a thin RuO_x layer formed on the Ru/TiN/doped poly-Si/Si stack structure was compared with that on the RuO_x/TiN/doped poly-Si/Si stack structure over the post-deposition annealing temperature ranges of 450–600°C. The Ru/TiN/poly-Si/Si contact system exhibited linear behavior at forward bias with a small increase in the total resistance up to 600°C. The RuO_x/TiN/poly-Si/Si contact system exhibited nonlinear characteristics under forward bias at 450°C, which is attributed to no formation of a thin RuO_x layer at the RuO_x surface and porous-amorphous microstructure. In the former case, the addition of oxygen at the surface layer of the Ru film by pre-annealing leads to the formation of a thin RuO_x layer and chemically strong Ru-O bonds. This results from the retardation of oxygen diffusion caused by the discontinuity of diffusion paths. In particular, the RuO_x layer in a nonstoichiometric state is changed to the RuO₂-crystalline phase in a stoichiometric state after post-deposition annealing; this phase can act as an oxygen-capture layer. Therefore, it appears that the electrical properties of the Ru/TiN/poly-Si/Si contact system are better than those of the RuO_x/TiN/poly-Si/Si contact system.