GaN-based FETs using Cat-CVD SiN passivation for millimeter-wave applications

We have found that SiN passivation by catalytic chemical vapor deposition (Cat-CVD) can significantly increase an electron density of an AlGaN/GaN heterostructure field-effect transistor (HFET). This effect enables thin-barrier HFET structures to have a high-density two-dimensional electron gas and leads to suppression of short-channel effects. We fabricated 30-nm-gate Al_0.4Ga_0.6N(8 nm)/GaN HFETs using Cat-CVD SiN. The maximum drain current density and extrinsic transconductance were 1.49 A/mm and 402 mS/mm, respectively. Current-gain cutoff frequency and maximum oscillation frequency of the HFETs were 181 and 186 GHz, respectively. These high-frequency device characteristics are sufficiently high enough for millimeter-wave applications.     

PECVD SiN及其在GaAs MESFET中的应用——第1部分:PECVD SiN的制备及其组分和键结构

叙述了PECVD SiN的制备、性能及其在GaAs场效应器件中的应用。第一部分叙述PECVD SiN的一般概念、设备及淀积条件,阐明其键结构以及它们与工艺条件的关系。第二部分叙述PECVD SiN性能及其与工艺条件的关系,着重叙述在GaAs器件中的应用和对器件性能的影响。     

基于槽形结构的c-CESL应变95nm栅NMOSFET性能增强技术

本文针对应变NMOSFET提出了一种基于槽型结构的应力调制技术。该技术可以利用压应变的CESL（刻蚀阻挡层）来提升Si基NMOSFET的电学性能,而传统的CESL应变NMOSFET通常采用张应变CESL作为应力源。为研究该槽型结构对典型器件电学性能的影响,针对95 nm栅长应变NMOSFET进行了仿真。计算结果表明,当CESL应力为-2.5 GPa时,该槽型结构使沟道应变状态从对NMOSFET不利的压应变（-333 MPa）转变为有利的张应变（256 MPa）,从而使器件的输出电流和跨导均得到提升。该技术具有在应变CMOS中得到应用的潜力,提供了一种不同于双应力线（DSL）技术的新方案。     

微机械氮化硅梁谐振式压力传感器

报导一种新型的电热激励、压阻拾振的氮化硅梁谐振式压力传感器。器件采用微电子机械加工技术和键合技术研制。谐振频率85kHz,空气中品质因素Q值接近1000,在真空中达到40000。采用闭环自激振荡方式测定压力传感器的压力特性,压力测试范围0－400kPa,灵敏度23．8Hz/kPa。     

深亚微米同步辐射x射线光刻技术

报道了我们制作深亚微米 x射线掩模的工艺和同步辐射 x射线曝光工艺 ,并报道了我们在北京同步辐射装置 (BSRF) 3B1 A光刻束线所获得的深亚微米 x射线光刻图形的实验结果     

Influence of an ammonia activation prior to the PECVD SiN deposition on the solar cell performance

Silicon nitride (SiN) from plasma-enhanced chemical vapour deposition is widely used in PV industry as an antireflection coating. In addition the large amount of hydrogen (of up to 25 at%) (J. Appl. Phys. 49 (1978) 2473) incorporated in the SiN layer can be driven into the solar cell during the contact firing step, leading to an excellent bulk passivation as demonstrated by several research institutes during the last decade (Proceedings of the 12th EC PVSEC, Amsterdam, The Netherlands, 1994, p. 1018). Despite these advantages sometimes a problem occurs during the firing of the SiN layer, called blistering. Supposing that the blistering effect can be influenced by the surface preparation we performed a short ammonia plasma activation step prior to the SiN deposition. This step results in no damage of the surface which is shown in the form of solar cell results and lifetime measurements. On the contrary a positive effect on lowly doped emitters is possible.     

Effect of hydrogen radical annealing on SiN passivated solar cells

Remote plasma was used for PE-CVD of SiN films and it was found that hydrogen radical (H^* ) annealing of c-Si cells with SiN films improved the efficiency of the cells. Cell efficiency of 21.8% was obtained by applying a SiN/SiO₂ double-layer structure on the emitter of a PERL-type solar cell. It was found that the H^* annealing has two effects: it reduces surface recombination velocity (SRV); and it degrades bulk-lifetime of p-type c-Si. To apply SiN practically, it is effective to use a rear n-floating or a triode structure. Reducing the exposed area of the p-type substrate by using n-type diffused layer increases the efficiency of solar cells.     

Application of Cat-CVD for ULSI technology

The ULSI technology has been following Moore's law into the sub-100 nm era, although several challenging technical issues must be resolved. This paper describes possible application of Cat-CVD for ULSI technology beyond the 45 nm node. Especially, Cat-CVD SiN film for a transistor gate sidewall and/or a pre-metallic liner layer, and removal of photo resist (ash) by Cat-induced hydrogen atoms in the interconnect structure with an extreme low-k material are mainly discussed.     

Characteristics of Si3N4/GaAs metal-lnsulator-semiconductor interfaces with coherent Si/Al0.3Ga0.7As interlayers

Si₃N₄/GaAs metal-insulator-semiconductor (MIS) interfaces with Si(10Å)/ Al_0.3Ga_0.7As (20Å) interface control layers have been characterized using capacitance-voltage (C-V) and conductance methods. The structure was in situ grown by a combination of molecular beam epitaxy and chemical vapor deposition. A density of interface states in the 1.1 × 10¹¹ eV^-1 cm^-2 range near the GaAs midgap as determined by the conductance loss has been attained with an ex situ solid phase annealing of 600°C in N₂ ambient. A dip quasi-static C-V demonstrating the inversion of the minority-carrier verifies the decent interface quality of GaAs MIS interface. The hysteresis and frequency dispersion of the MIS capacitors were lower than 100 mV, some of them as low as 50 mV under a field swing of about ±2 MV/cm. The increase of the conductance loss at higher frequencies was observed when employing the surface potential toward conduction band edge, suggesting the dominance of faster traps. Self-aligned gate depletion mode GaAs metal-insulator-semiconductor field-effect transistors with Si/Al_0.3Ga_0.7As interlayers having 3 μm gate lengths exhibited a transconductance of about 114 mS/mm. The present article reports the first application of pseudomorphic Si/ Al_0.3Ga_0.7As interlayers to ideal GaAs MIS devices and demonstrates a favorable interface stability.     

W7SiN高性能高速钢热处理工艺与切削性能试验研究

对W／SiN钢Φ17mm材料,通过不同热处理工艺参数进行了工艺试验,优选热处理工艺参数并制作几种刀具,与M2钢刀具进行了切削对比试验。