On the formalization and reuse of scientific research

The reuse of scientific knowledge obtained from one investigation in another investigation is basic to the advance of science. Scientific investigations should therefore be recorded in ways that promote the reuse of the knowledge they generate. The use of logical formalisms to describe scientific knowledge has potential advantages in facilitating such reuse. Here, we propose a formal framework for using logical formalisms to promote reuse. We demonstrate the utility of this framework by using it in a worked example from biology: demonstrating cycles of investigation formalization [F] and reuse [R] to generate new knowledge. We first used logic to formally describe a Robot scientist investigation into yeast (Saccharomyces cerevisiae) functional genomics [f₁]. With Robot scientists, unlike human scientists, the production of comprehensive metadata about their investigations is a natural by-product of the way they work. We then demonstrated how this formalism enabled the reuse of the research in investigating yeast phenotypes [r₁ = R(f₁)]. This investigation found that the removal of non-essential enzymes generally resulted in enhanced growth. The phenotype investigation was then formally described using the same logical formalism as the functional genomics investigation [f₂ = F(r₁)]. We then demonstrated how this formalism enabled the reuse of the phenotype investigation to investigate yeast systems-biology modelling [r₂ = R(f₂)]. This investigation found that yeast flux-balance analysis models fail to predict the observed changes in growth. Finally, the systems biology investigation was formalized for reuse in future investigations [f₃ = F(r₂)]. These cycles of reuse are a model for the general reuse of scientific knowledge.     

Design of a PLL with improved locking range and its biomedical applications

This paper describes a phase locked loop employing a low voltage VCO using modified ECL inverter cells. The VCO circuit employed, features a positive feed back scheme to improve the operating frequency. The phase detector used in the PLL also uses a positive feedback scheme to improve the locked range and to reduce supply voltage of operation of the entire circuit. An improvement of locked range of around 35% was obtained from circuit simulation (using PSPICE) as well as from practical circuit, using discrete components. The minimum supply voltage required here is 2.5 volts. Some biomedical applications of this PLL are also proposed.     

A System-layer Infrastructure for SoC Diagnosis

During IC manufacturing phase, discriminating between good and faulty chips is not enough. In fact, especially in the first phase of the production of a new device, a complete understanding of the possible failures is quickly required to ramp up production yield. For test engineers, dealing with the manufacturing test of Systems-on-chip (SoCs) means to tackle the extraction of diagnostic data from faulty chips. Another equally important aim of diagnosis, in a later step of a product lifecycle, is to find the real root cause of silicon misbehaviors for field returns. At the core test layer, the adoption of diagnosis-oriented Design-for-Testability structures is almost mandatory and many solutions have been worked out for several types of cores; diagnosis data retrieval often consists in the execution of a set of self-test procedures whose application order and/or customization may depend on the obtained results themselves. This paper details the characteristics of a system-layer test architecture able to manage efficiently SoC self-diagnostic procedures. This architecture is composed of a diagnosis-oriented Test Access Mechanism (TAM) and an Infrastructure-IP owning enough intelligence to automatically manage core diagnostic procedures. Both of them have been designed in compliance with the IEEE 1500 Standard for Embedded Core Test and exploit the characteristics of Self-Test structures inserted for the diagnosis of memory, processor and logic cores. This approach to SoC diagnosis minimizes ATE memory requirements for pattern storage and drastically speeds up the complete execution of diagnostic procedures. Experimental results highlight the convenience of the approach with respect to alternative ATE driven diagnosis procedures, while resorting to negligible area overhead.

离散时间区间时序逻辑可满足性的判定

目前还没有模型检查的方法自动检测模型是否满足时间区间时序逻辑描述的性质.我们约束时间域到离散时间,证明了离散时间区间时序逻辑的可满足性是可判定的,因而是可模型检查的.提出了时间正则图模型,通过从离散时间区间时序逻辑到时间正则图的构造,提出了基于该逻辑的判定算法,该算法可以推广到其它的时序逻辑模型检查,并优于现有的基于自动机的时序逻辑判定方法.     

面向商业智能的ETL模型研究综述

ETL(extra,transform,load)是数据仓库的重要组成部分。ETL过程是一个复杂的过程,从源数据中抽取,转换,装载到数据仓库的过程。文中通过从两个不同角度来建模,对ETL过程进行概念建模和逻辑建模。概念建模主要研究整个ETL过程概念和属性的内在属性,而逻辑建模主要研究是ETL工作流。最后,提出一个从概念模型映射到逻辑模型的转换算法。     

空对空多目标攻击载机攻击航线求解逻辑

介绍了空对空多目标攻击载机攻击航线的基本要求、航线选择和求解方法,以及载机航线、瞄准偏差、操纵指令的计算逻辑图.同时还介绍了多目标攻击"可能攻击扇形区"交集的概念和在载机航线求解中的应用等问题.     

结合逻辑模拟和布尔可满足性的设计错误诊断方法

在集成电路设计验证与调试过程中,逻辑错误诊断工具通常会给出一定数量的候选错误区域,然后通过特定的算法尽可能多地减少候选区域,以方便错误的准确定位。在此提出一种结合模拟与布尔可满足性（SAT）的错误诊断方法．用于提高错误诊断准确性。该方法首先使用模拟方法对候选的错误区域逐一进行判断,对于不能由模拟方法判别的候选区域,使用基于SAT的形式化方法进一步判断。针对ISCAS’85电路的实验结果表明,该方法具有较高的错误诊断准确性和效率。     

中频解调电路中的I^2C总线接口电路

为了简化中频解调电路的外围接口电路,缩小芯片面积,提高芯片的通用性和可靠性,在I^2C总线数据传输协议的基础上,设计一个兼容I^2C协议的中频解调接口电路。为了防止芯片地址冲突,增加了4位地址选择位,并重点对接口电路的状态机与控制逻辑进行优化设置。仿真结果表明,该电路功能正确,可靠性高,可广泛用于TV,VTR,PC,STB等方面。     

数字技术在广播电视发射机中的应用

在CSD-1-Ⅰ-1型Ⅰ波段1kW单通道电视发射机中,数字技术被应用于逻辑控制系统,常见的数字集成电路有H005（H004）双与非门电路、JK触发器等,主要介绍其应用原理。     

阈算术代数系统及多值电流型CMOS电路设计

该文根据电流信号易于实现算术运算的特点,定义了阈算术运算及非负运算,建立了一个适合于电流型电路设计的阈算术代数系统,并在阈算术代数系统中定义和图为阈算术函数的图形表示。在此基础上,通过三值电流型CMOS电路的设计实例,阐述了运用和图将逻辑函数转化为阈算术函数的电流型CMOS电路设计方法。采用TSMC 0.18m CMOS工艺参数的HSPICE模拟结果表明,所设计的电路具有正确的逻辑功能。阈算术代数系统的提出及和图的运用为电流型电路设计提供了一种新的简单有效的方法。