TFT LCD中Γ校正的系统设计与实现

以分辨率240RGB×320的小尺寸彩屏TFT LCD为研究对象,针对驱动系统传送的视频数据不能正确反映亮度在大脑中形成的感觉问题,进行Γ校正电路设计。借助ORCAD PSPICE仿真软件,并采用TSMC 0.25μmMixed-Signal Salicide工艺完成电路仿真设计。仿真结果表明:系统设计的电路很好地实现了幅度调节、斜率调节、以及微调节功能。     

利用Cortex-M3实现同步电动机失步保护的装置

提出一种基于Cortex-M3处理器的失步保护器的设计方法。硬件设计上,介绍了模块间的硬件连接情况,软件上,介绍了A／D采样的实现情况。该保护器采用STM32F103ZE作为微控制器,采用MicroSD卡存储采集的数据,通过USB接口向PC机输送实时数据。该系统的软件使用RealViewMDK开发。     

Q-learning算法及其在囚徒困境问题中的实现

Ｑ－ｌｅａｒｎｉｎｇ是一种优良的强化学习算法。该文首先阐述了Ｑ－ｌｅａｒｎｉｎｇ的基本学习机制,然后以囚徒困境问题为背景,分析、对比Ｔ Ｑ－ｌｅａｒｎｉｎｇ算法与ＴＦＴ算法,验证了 Ｑ－ｌｅａｒｎｉｎｇ算法的优良特性。     

Back‐channel‐etched thin‐film transistor using c‐axis‐aligned crystal In–Ga–Zn oxide

Our crystalline In–Ga–Zn oxide (IGZO) thin film has a c‐axis‐aligned crystal (CAAC) structure and maintains crystallinity even on an amorphous base layer. Although the crystal has c‐axis alignment, its a‐axis and b‐axis have random arrangement; moreover, a clear grain boundary is not observed. We fabricated a back‐channel‐etched thin‐film transistor (TFT) using the CAAC‐IGZO film. Using the CAAC‐IGZO film, more stable TFT characteristics, even with a short channel length, can be obtained, and the instability of the back channel, which is one of the biggest problems of IGZO TFTs, is solved. As a result, we improved the process of manufacturing back‐channel‐etched TFTs.     

a—SiTFTLCD象素电压跳变特性研究

提出了α-Si TFT 栅源(源端与象素电极相连)电容不仅为栅源电极间交迭所产生的寄生电容 C_(gsp),还应包括源端沟道与栅电极间的本征电容 C_(gsi)。并以缓变沟道近似模型推导了 C_(gsi)的数学表达式。该式计算结果表明:TFT 开态下C_(gsi)为栅介质电容的一半。在此基础上求出了象素跳变电压ΔV_p 的精确计算公式。该公式圆满解释了传统的ΔVp 公式所不能解释的几个实验结果,从而澄清了对ΔVp 产生机理所存在的模糊认识。     

多晶硅有源矩阵液晶显示器

本文首先就用来制造有源矩阵液晶显示器的非晶硅和多晶硅材料作了性能比较,然后描述了多晶硅薄膜晶体管阵列的制造方法,以及在制造方法上取得的进展。     

Laser Recrystallization of Polycrystalline Silicon in Recessed Structures

The pulsed-laser recrystallization of polysilicon in recessed structures, consisting of a silicon film deposited on a patterned oxide layer on a heat sink, is investigated for the first time. The different thermal environments created by the recess area, when compared to those outside this area, causes the recessed silicon to cool first. The different cooling rates in the continuous silicon film creates lateral temperature gradients, producing large elongated grains. Additionally, the recessed structure can lead to different film microstructures within the recessed area compared to outside this area. This structure is therefore capable of grain engineering different microstructures for polysilicon.     

氢化非晶硅薄膜晶体管的静态特性研究

发展了一种研究a－Si：HTFT静态特性的新方法。从a－Si材料的带隙态密度适配参数分布函数出发，采用Shockley－Read-Hall统计描述，发展了一种局域态电行密度统一模型，该模型同时考虑了带尾局域态和缺陷局域态的作用。提出并分析了沟道区有效温度参数的概念，在此基础上，推导出了a－Si：HTFT电流—电压特性的解析表达式。其理论值与实验值符合很好。并详细分析了a－Si材料参数对TFTN态特性的影响。     

A novel low‐power gate driver architecture for large 8 K 120 Hz liquid crystal display employing IGZO technology

A novel low‐power gate driver architecture was developed for large 8 K 120 Hz liquid crystal display panel. For this application, not only high‐speed driving but also low power consumption is required. We employed a high mobility In‐Ga‐Zn‐O, dual V_GL level driving method, and gate driver circuit driven by DC supply. The simulation results show that our proposals meet 8 K 120 Hz driving requirements. Also, we have fabricated a prototype panel and confirmed both high‐speed driving and low power consumption.     

Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.