基于数字孪生的测试性验证技术

针对型号测试性验证工作中存在的验证周期长、验证时机滞后、验证环境受限等问题,开展了基于数字孪生技术的测试性验证技术研究,重点关注数字孪生技术框架和关键技术研究,包括基于数字孪生驱动的故障模式分析、基于数字孪生驱动的故障模式空间模拟、基于数字孪生驱动的故障模式分配与注入、基于数字孪生驱动的数据融合技术,以期实现装备全生命周期的测试性验证与增长。形成一套基于数字孪生驱动的测试性验证流程及方法,用于指导新研产品的测试性验证工作。     

一种行为级可测试性综合方法*

伴随着高层次综合技术的普及和深入,高层次可测试性综合技术引起了广泛的关注。在简单介绍当前可测试性综合技术的现状后,提出了采用“VHDL进,VHDL出”的方式进行行为级可测试性综合的流程,并提出了一个新的行为级可测试性分析算法,然后讨论了测试点的选择、可测试结构的规范化描述和自动插入的技术与方法。     

Finite state machine synthesis with embedded test function

We propose a synthesis for a testability method in which the test function is incorporated into the state diagram of the finite state machine (FSM). The test function is specified as an FSM with the same number of state variables as the given object machine. Based upon the chosen test methodology, a variety of test functions can be defined. As an illustration, we construct a test machine in which each state is uniquely set and observed by an input sequence no longer than log _k n, wheren is the number of states and the integerk is a design parameter. The state transition graph of the test machine is superimposed on the state graph of the object function such that a minimal number of new transitions are added. State assignment, logic minimization, and technology mapping are carried out for the combined graph. By design, the embedded test machine is fully testable. Also, since the test machine can control all memory elements, the circuit is effectively tested by a combinational circuit test generator. Scan register is shown to be a special case in this methodology.     

Estimating software testing complexity

ContextComplexity measures provide us some information about software artifacts. A measure of the difficulty of testing a piece of code could be very useful to take control about the test phase.ObjectiveThe aim in this paper is the definition of a new measure of the difficulty for a computer to generate test cases, we call it Branch Coverage Expectation (BCE). We also analyze the most common complexity measures and the most important features of a program. With this analysis we are trying to discover whether there exists a relationship between them and the code coverage of an automatically generated test suite.MethodThe definition of this measure is based on a Markov model of the program. This model is used not only to compute the BCE, but also to provide an estimation of the number of test cases needed to reach a given coverage level in the program. In order to check our proposal, we perform a theoretical validation and we carry out an empirical validation study using 2600 test programs.ResultsThe results show that the previously existing measures are not so useful to estimate the difficulty of testing a program, because they are not highly correlated with the code coverage. Our proposed measure is much more correlated with the code coverage than the existing complexity measures.ConclusionThe high correlation of our measure with the code coverage suggests that the BCE measure is a very promising way of measuring the difficulty to automatically test a program. Our proposed measure is useful for predicting the behavior of an automatic test case generator.     

基于电路状态信息和冲突分析的部分扫描设计

该文提出了一种割断关键回路的方法来选择扫描触发器。该方法在选择一定数量的扫描触发器后,采用逻辑模拟更新电路的状态信息,这样可以得到更为精确的可测试性信息。当电路中的关键回路割断后,转向消除冲突的处理,而不是降低时序深度。该方法致力于消除冲突,并使用了一种基于冲突分析的测度conflict。足够的实验结果表明该方法是非常有效的。     

软件内建自测试中测试点的设置及个数的研究

软件内建自测试思想来自于硬件内建自测试。其中测试点设置是软件内建自测试系统的核心模块之一,主要借助程序插装技术收集动态测试信息和控制程序流程。具体讨论了插装库的设计、实现以及测试点个数的统计。     

电路结构特殊点及可测性研究

电路结构上一些特殊点对于电路的测试影响很大,通过对电路结构上一些特殊点的性质、作用、它们之间的相互关系,以及电路结构可测性与这些点的关系进行研究,按照它们的作用大小进行排序,从而加快确定性测试码的生成速度,减少回溯次数和缩短回溯时间,提高其可测性。     

一个新的信号概率计算方法

本文提出了一种改进的加权平均算法ＩＷＡＡ，针对加权平均算法ＷＡＡ，ＩＷＡＡ引入了最小重汇聚扇出源ＭＲＦＳ的概念，用于信号概率的计算，并取得了较为理想的结果。