Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability

Current‐oriented operational amplifier (OpAmp) design has been common for its orderly current‐to‐speed tradeoff. However, for high‐precision or high‐linearity applications, increasing the current does not help much, as the supply voltage (V_DD) and intrinsic gain of the MOSFETs in ultra‐scaled CMOS technologies are very limited. This paper introduces voltage‐oriented circuit techniques to address such limitations. Specifically, a 2xV_DD‐enabled recycling folded cascade (RFC) OpAmp is proposed. It features: (1) current recycling to enhance the effective trans conductance by 4x with no extra power; (2) transistor stacking to boost the output resistance by one to two orders of magnitude; and (3) V_DD elevating to enlarge the linear output swing by 4x. Comparing with its 1xV_DD RFC and FC counterparts, the proposed solution achieves 20‐dB higher DC gain (i.e. 72.8 dB) in open loop and 20‐dB lower IM3 (i.e., –76.5 dB) in closed loop, under the same power budget of 0.6 mW in a 1‐V General Purpose 65‐nm CMOS process. In many applications, these joint improvements in a single stage are already adequate, being more power efficient (i.e. less current paths), stable (i.e. more phase margin), and compact (i.e. no frequency compensation) than multi‐stage OpAmps. Voltage‐conscious biasing and node‐voltage trajectory check ensure the device reliability in both transient and steady states. No specialized high‐voltage device is necessary. Copyright © 2012 John Wiley & Sons, Ltd.     

A low‐power four‐stage amplifier for driving large capacitive loads

A four‐stage amplifier with a new and efficient frequency compensation topology is presented in this paper. The new compensation scheme applies a Miller capacitor as the main negative feedback, a resistor and a capacitor in series as a load for one of the intermediate stages, and two feedforward paths. In order to design the amplifier and acquire circuit parameters, small signal analyses have been carried out to derive the signal transfer function and the pole‐zero locations. The proposed amplifier was designed and implemented in a standard 90 nm CMOS process with two heavy capacitive loads of 500 pF and 1 nF. The simulation results show that when driving a 500 pF load, the amplifier has a gain‐bandwidth product of 18 MHz consuming only 40.9 μW. With a 1 nF capacitive load, the proposed amplifier achieves 15.1 MHz gain‐bandwidth product and dissipates 55.2 μW from a single 0.9 V power supply. Copyright © 2013 John Wiley & Sons, Ltd.     

利用SuPA给手持设备射频功率放大器供电

在手持设备中给射频功放供电一直是一个比较难做的设计,因为一方面需要提高射频功放的工作效率用来延长电池的工作时间,另一方面又不能在提高工作效率的同时降低功放的工作性能,所以必须为其提供一个满足要求的高效直流电源。常规的方式,是将功放的电源端与电池直接连接供电,但是这种工作模式会使得功放的工作效率很低,不能满足高效低功耗要求。德州仪器公司推出的SuPA(Supply for Power Amplifier)系列的DC-DC产品,从工作机理上做了创新,采用平均功率跟踪(Average Power Track)技术和包络跟踪技术(Envelop Tracking),优化了射频功放工作时功率消耗,从而提高了功放的工作效率,延长了电池的工作时间。本文着重阐述平均功率跟踪技术的工作原理和SuPA的应用设计,从而方便设计工程师能够快速地理解和应用此项技术,实现高效的功放电源设计。     

一种简单可靠的恒压恒频交流电源

本文介绍一种简单可靠的恒压恒频交流电源装置,它由直流电动机-交流发电机组、自动电压调节器AVR及自动频率调节器AFR组成.AVR和AFR中采用磁放大器作为比较放大和移相触发环节,具有线路简单、运行可靠的优点.文章详细介绍了AVR和AFR的构成、各环节的工作原理及性能.     

电磁轴承系统中的功率放大器

就电磁轴承系统线性和开关功放各主要参数的设计方法及这些参数与电磁轴承系统的关系作一讨论,提出了设计中的一般原则和注意事项     

60GHz单级功率放大器的设计

该文探讨了60 GHz 功率放大器的设计方法,设计并测试了基于0．07μm GaAs 工艺的60 GHz毫米波单片功率放大器,该放大器采用共源结构,单级放大,工作电压为1．2 V,工作电流为27 mA,在62．2 GHz 时有最大小信号增益4．9 dB,60 GHz 时仿真的输出1 dB 压缩点功率为12 dBm。     

C波段GaN HEMT功率放大器设计

该文介绍了一款应用于38 GHz的大功率超宽带功率放大器。电路设计中采用了键合线连接裸片与微带电路,并对该部分单独进行电磁场仿真。采用渐变微带线的方法实现了宽带匹配,通过HFSS与ADS的联合仿真优化设计,完成了大功率宽频带的功率放大器设计和仿真过程,仿真结果表明在频率38 GHz范围内增益（8．5＆#177;1） dB,1 dB压缩点输出功率为48 dBm最大饱和功率为49．5 dBm。     

巨磁致伸缩材料磁机械耦合系数的测量

根据磁机械耦合系数的测量原理，利用锁相放大器建立了磁机械耦合系数测量系统，并应用该系统测量了巨磁致伸缩材料的磁机械耦合系数。测试结果表明，采用锁相放大器技术所测得的磁机械耦合系数是准确可靠的。     

闭环系统中反馈回路的微小信号处理方法

针对闭环控制系统中当反馈回路信号极其微弱时暴露出的性能缺陷,通过电路结构和数学模型两种方法分析了微弱反馈回路信号对于闭环系统控的制稳定度和灵敏度的影响,提出了微小反馈信号时如何保持闭环控制稳定性和灵敏度的分级放大方法及参数设计。     

光纤放大器的发展及展望

简要介绍光纤放大器的原理,类型,发展现状及展望,并着重讲述了光纤通信网有着密切联系的掺饵光纤放大器（ＥＤＦＡ）的原理,类型及应用前景。