RFID在候机室管理系统中的应用研究

通过RFID技术、新RFID中间件工具Oracle Sensor Edge Server和Stream Dispatcher，CAVIP系统实时以非接触方式获取旅客位置信息，定位旅客在候机室中的位置，进而提高服务质量。CAVIP系统通过RFID中间件可以做到及早过滤采集到的无效RFID数据，有效保护RFID网络的投资，协调不同来源的RFID设备，而且通过创新性地使用Oracle Stream 和触发器可以做到使企业应用系统不知道RFID的存在，使企业实施RFID高效快速且易于实现。     

J2EE应用中任务的动态调度

本文概括的描述了应用系统中任务调度框架的发展。从调度思想,触发模式,调度的一些基本原则等方面阐述了任务调度的体系结构及其内容。接着对其在应用中的部署进行了优化,得出了改进和优化以后的任务调度构架。最后还提出了与数据库技术相结合的技术解决方案。     

移动通信数据备份查询的一种新方法

移动通信数据的海量增加,对以前数据的查询显得束手无策.现在普遍采用的是把以前的数据整体备份到磁带或光盘上,文中提出一套切实可行的数据备份和整理方案,基于应用程序和过程、触发器机制把原始数据库数据转换到备份查询数据库中,既保证了数据库系统的运行性能,又不损失系统的历史数据,同时起到数据备份功能,在完整备份并删除相应旧的数据的基础上,又能对以前的数据进行查询和统计,延长数据的实际存活时间.     

可控硅移相触发模块设计

对电力电子技术实验设备中由K J004组成的触发器件提出一种新的设计,用M CS51系列单片机设计的一种单相桥式触发模块,采用单片机控制并显示所要导通的导通角,通过D/A转换得出K J004触发器件的移相控制信号,以实现其移相控制电压目的。系统设计电路简单,容易实现,成本低。极大地提高晶闸管导通角控制精度,方便使用。     

过程和触发器的简单实现

本文介绍了如何利用Delphi与SQL server2000的结合。通过Delphi组件实现数据库的存储，及编写触发器的过程和方法。     

数字式直流电机调速器的硬件设计

介绍了全数字直流电机调速器的设计思想及各功能模块的具体实现方案。首先介绍了系统的总体结构,接着依次详细说明了各个功能模块的设计思想与实现方案。     

菲利蒲真空X射线光谱仪PW1410的故障维修

本文介绍X射线光谱仪的维修体会     

数字存储示波器时基及触发特性的精确评价

本文提出一种数字存储皮器时基和触发特性的精确评价方法,通过使用正弦波拟合法,其时基准确度,触发沿斜率,触发电平不确定度,触发延时误差以及触发沿晃动被精确评价;详细描述了其测量原理,并给出了误差分析和实验例证,验证了该方法及过程的可行性。     

Temperature-dependence of steady-state characteristics of SCR-type ESD protection circuits

Experimental analysis of the temperature-dependent I–V characteristics of various SCR (Silicon-Controlled Rectifier) electrostatic discharges (ESD) protection circuits have been carried out. These circuits include diode-chain-triggering SCR (DCTSCR), low-voltage zener diode trigger SCR (ZDSCR), low-voltage trigger SCR (LVTSCR) and gate-coupled low-voltage trigger SCR (GCSCR) circuits. The ZDSCR uses the zener breakdown mechanism of a reverse-biased p⁺–n⁺ diode as a trigger mechanism, the DCTSCR uses the current flowing through forward-biased diode chain as a trigger mechanism, the LVTSCR uses the grounded-gate MOSFET breakdown current as the trigger mechanism and the steady-state I–V characteristics of GCSCR also uses the avalanche breakdown as a triggering mechanism. The trigger voltage can decrease or increase with increasing temperature depending upon the triggering mechanism used in the circuit, however the holding voltages of these SCRs decrease with increasing temperature.     

High-speed,fixed-latency serial links with Xilinx FPGAs简

High-speed, fixed-latency serial links find application in distributed data acquisition and control systems, such as the timing trigger and control （TTC） system for high energy physics experiments. However, most high-speed serial transceivers do not keep the same chip latency after each power-up or reset, as there is no deterministic phase relationship between the transmitted and received clocks after each power-up. In this paper, we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays （FPGAs）. First, we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver. Second, we use the internal alignment circuit of the transceiver and a digital clock manager （DCM）/phase-locked loop （PLL） based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver. The test results of the link latency are shown. Compared with existing solutions, our design not only implements fixed chip latency, but also reduces the average system lock time.