Modeling and analysis method of fractional-order buck–boost converter

In this paper, the equivalent small parameter method (ESPM) is used to establish the nonlinear mathematical model of the fractional-order buck–boost converter in continuous current mode (CCM), and the analytical expression of approximate steady-state period of converter state variable is obtained by using equivalent small parameter method and combining with harmonic balance principle. The Matlab/Simulink is used to construct the fractional-order capacitance and inductance and to build the circuit model as well as the simulation model of fractional-order buck–boost converter. Moreover, the simulation results of Oustaloup circuit model and numerical simulation model are compared with those of ESPM model to verify the validity and accuracy of the ESPM. The model is simulated by changing the orders of the capacitor and inductor to obtain the influence rule of the order of fractional element on harmonic characteristics of the state variables.     

Analysis and control of a single switch wider step-down gain DC–DC converter for low-voltage applications

This paper presents a point-of-load transformerless DC–DC converter having a wider step-down conversion ratio. In comparison with quadratic/stacked buck converter variants, the presented topology exhibits nonpulsating source current, more effective switch utilization at small voltage gains, and reduced current stress on components. Its comprehensive steady-state analysis is carried out under continuous and discontinuous modes of inductor currents, and design criteria to select L-C components are established. State variable dependency feature in the topology, imposing a reduced fourth-order dynamics, is discussed and subsequently verified from its average model. A fixed frequency sliding mode controller is then designed with a step-by-step evaluation of sliding surface existence, reachability, and stability conditions. The equivalent control law devised in this scheme is duly constituted from source side inductor current dynamics and load voltage error information, so it facilitates simple realization as well as better transient response. Remarkable operational characteristics of the presented converter are studied analytically and demonstrated with experimental observations on a laboratory prototype.     

双有源桥DC-DC变换器升降压功率特性优化控制

双有源桥DC-DC变换器工作在升压、降压状态下时,在传统单移相控制下,电压的不匹配程度会影响变换器的超前桥、滞后桥以及电感上的功率分布情况,进而增加变换器的通态损耗。引入内移相角的双重移相控制可以改变输入、输出侧的电压波形,进而优化流过超前桥、滞后桥的无功功率,在改变变换器的功率特性的同时增加了控制的自由度和灵活性。在此基础上提出了变换器工作在升压、降压状态下,以电感上的无功功率为优化目标的双重移相控制策略,减小了变换器的整体无功功率和通态损耗,从而提高变换器的效率。最后通过试验验证了该双重移相控制方式的有效性和优越性。     

一种高增益双向准Y源DC-DC变换器

针对传统双向DC-DC变换器电压增益小、传输效率低等问题,提出了一种改进型高增益双向准Y源DC-DC变换器电路拓扑,通过调节双向功率开关管的导通占空比和耦合电感的匝数比,实现功率双向传输的目的。电路拓扑结构简单,传输效率高,具有连续的输入电流,绕组匝数比设计灵活,进一步提高了电压增益,调压范围更宽。首先对电路的拓扑结构和工作原理进行了分析,并通过数学公式推导证明了其正、反向2种工作状态下的升/降压性能;然后用Matlab/Simulink软件进行了仿真分析;最后搭建实验样机进行验证,仿真和实验结果均证实了电路拓扑的可靠性和优越性。     

Fast‐transient DC‐DC converter using a high‐performance error amplifier with a rapid output‐voltage control technique

This letter presents a method for improving the transient response of DC‐DC converters. The proposed technique replaces the conventional error amplifier with a combination of two different amplifiers to achieve a high loop gain and high slew rate. In addition, a rapid output‐voltage control circuit is employed to further reduce the recovery time. The proposed technique was applied to a four‐phase buck converter, and the chip was implemented using a 0.18‐μm CMOS process. The switching frequency of each phase was set at 2 MHz. Using a supply voltage of 2.7–5.5 V and an output voltage of 0.6–1.5 V, the regulator provided up to 2‐A load current with maximum measured recovery time of only 6.2 and 6.5 μs for increasing and decreasing load current, respectively. Copyright © 2017 John Wiley & Sons, Ltd.     

A new bridgeless buck PFC rectifier

In this study, a new bridgeless buck power factor correction (PFC) rectifier is presented. The proposed buck PFC rectifier is designed to operate in the discontinuous conduction mode (DCM). Because of the DCM operation, the control scheme of the proposed buck PFC rectifier is simple and easy, and the reverse recovery problem of the diodes can be alleviated. Because the input current follows the input voltage naturally, the current loop circuit is not required. Thus, only the traditional voltage‐mode control is employed to sense the output voltage, and a suitable control effort for the proposed buck PFC rectifier is generated to drive the power switches. Consequently, the output voltage of the proposed buck PFC rectifier can be kept at a desired value. Finally, the mathematical deductions and experimental results are provided to verify the effectiveness of the proposed bridgeless buck PFC rectifier. Copyright © 2016 John Wiley & Sons, Ltd.     

DC analysis and design of a PWM buck converter operated as a dynamic power supply

Modern energy transmission and signal reproduction techniques rely upon power amplifiers that must operate with high efficiency. An increasingly popular technique for addressing this problem involves replacing the fixed power amplifier supply voltage V _{D D} with a controlled, variable voltage provided by a dynamic power supply. Although pulse‐width modulated dc‐dc buck converters typically function as fixed‐output supplies, this paper provides new theoretical dc analysis for operation wherein the output voltage is controlled and continuously variable over a wide range. A design procedure for the variable‐output buck converter is derived. Key device parameters affecting converter speed and efficiency are identified. The dc analysis and design procedure are verified experimentally, with calculated and measured parameters shown to be in good agreement. Copyright © 2016 John Wiley & Sons, Ltd.     

Integrated mixed signal control IC for 500-kHz switching frequency buck regulator

The main purpose for this work is to study the challenges of designing a digital buck regulator using pipelined analog to digital converter (ADC). Although pipelined ADC can achieve high sampling speed, it will introduce additional phase lag to the buck circuit. Along with the latency brought by processing time of additional digital circuits, as well as the time delay associated with the switching frequency, the closed loop will be unstable; moreover, raw ADC outputs have low signal-to-noise ratio, which usually need back-end calibration. In order to compensate these phase lag and make control loop unconditional stable, as well as boost up signal-to-noise ratio of the ADC block with cost-efficient design, a finite impulse response filter followed by digital proportional-integral-derivative blocks were designed. All these digital function blocks were optimised with processing speed. In the system simulation, it can be found that this controller achieved output regulation within 10% of nominal 5 V output voltage under 1 A/µs load transient condition; moreover, with the soft-start method, there is no turn-on overshooting. The die size of this controller is controlled within 3 mm² by using 180 nm CMOS technology.     

High-accuracy current sensing circuit with current compensation technique for buck–boost converter

A novel on-chip current sensing circuit with current compensation technique suitable for buck–boost converter is presented in this article. The proposed technique can sense the full-range inductor current with high accuracy and high speed. It is mainly based on matched current mirror and does not require a large proportion of aspect ratio between the powerFET and the senseFET, thus it reduces the complexity of circuit design and the layout mismatch issue without decreasing the power efficiency. The circuit is fabricated with TSMC 0.25 µm 2P5M mixed-signal process. Simulation results show that the buck-boost converter can be operated at 200 kHz to 4 MHz switching frequency with an input voltage from 2.8 to 4.7 V. The output voltage is 3.6 V, and the maximum accuracy for both high and low side sensing current reaches 99% within the load current ranging from 200 to 600 mA.     

超快速加载Buck变换器设计

为了提高VRM的加载响应速度,该文分析了传统Buck变换器的最优加载过程,并基于传统Buck变换器提出了双输入Buck变换器电路方案,说明了其稳态工作过程和加载运行过程,以最优加载阈值为依据给出了附加电源的切换条件,并做了仿真对比研究.仿真和试验结果表明双输入Buck变换器较传统Buck变换器具有更快加载响应速度和更小输出电压跌落,且结构简单,易于设计和实现,适用于VRM主电路.