A High-Precision Time Handling Library

An appropriate assessment of end-to-end network performance presumes highly efficient time tracking and measurement with precise time control of the stopping and resuming of program operation. In this paper, a novel approach to solving the problems of highly efficient and precise time measurements on PC-platforms and on ARM-architectures is proposed. A new unified High Performance Timer and a corresponding software library offer a unified interface to the known time counters and automatically identify the fastest and most reliable time source, available in the user space of a computing system. The research is focused on developing an approach of unified time acquisition from the PC hardware and accordingly substituting the common way of getting the time value through Linux system calls. The presented approach provides a much faster means of obtaining the time values with a nanosecond precision than by using conventional means. Moreover, it is capable of handling the sequential time value, precise sleep functions and process resuming. This ability means the reduction of wasting computer resources during the execution of a sleeping process from 100% （busy-wait） to 1-1.5%, whereas the benefits of very accurate process resuming times on long waits are maintained.     

白山发电厂时钟统一对时系统建设

时间同步系统作为智能化水电厂基础支撑系统,在智能化水电厂建设中发挥着基础服务作用。主要介绍了白山发电厂建设对时系统的结构及主要特点,首次采用PTP授时作为备用信号输入,增加了整个时钟系统的稳定性,提高了系统的授时精度,实现远程异地授时。     

基于LFSR的钟控密钥流生成器

本文提出了一种基于LFSR的钟控密钥流生成器。该生成器通过一个钟控线性移位寄存器从15个级数是两两互素的线性移位寄存器中控制选取10个,将所选出的各线性移位寄存器生成的m序列相加,然后输出,从而达到了伪随机序列周期扩大的目的。本文还对密钥流生成器的线性复杂度、均匀性、相关性以及游程特性进行了分析。分析表明,该生成器生成序列的周期能达到2128,而且有较大的线性复杂度和良好的相关性和均匀性。认为该序列可以作为密钥流序列进行加密。通过钟控的方式随机选取用于相加的m序列,增加了密钥流序列的条数。此外,本文还给出了该生成器的具体实现算法,有一定的实用价值。     

A single layer zero skew clock routing in X architecture

With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture (called Planar-CRX). Our Planar-CRX method integrates the extended deferred-merge embedding algorithm (DME-X, which extends the DME algorithm to X architecture) with modified Ohtsuki’s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm. Supported in part by the National Natural Science Foundation of China (Grant No. 60876026), and the Specialized Research Fund for the Doctoral Program of Higher Education (Crant No. 200800030026)     

PLC定时计数功能在住宅小区自动控制中的应用研究

以某住宅小区的自动控制为例,利用三菱PLC的定时计数功能组成电子时钟,按预先设定的时段定时启动各控制程序,完成相应的控制功能,取得了很好的效果,对其它自动控制也有一定的借鉴作用。     

基于延迟合并嵌入的带障碍的时钟树布线算法

提出一种在带障碍情况下,基于延迟合并嵌入方法的时钟树构建算法,并在时钟树构造过程中引入了轨迹图以保证布线可以绕过障碍．该算法以已知障碍为布线约束,首先自底向上计算时钟树内部节点的可能位置,然后自顶向下确定每个节点的确切位置．实验结果表明,该算法能够正确、有效地实现有障碍存在时的时钟树布线,线长优化率超过7％．     

一种增强型PTP光纤级联精细时频同步方法

该文提出了一种增强型PTP光纤级联精细时频同步方法,该方法以PTP同步技术为基础,结合同步以太网时钟传递技术和基于数字双混频时差法的多级级联精细时钟同步技术,对PTP技术进行改进和增强,然后基于该方法,通过多级时频设备光纤级联的形式实现多节点、大跨度、网络化的时频信号传递与同步输出,并解决多级级联情况下同步精度会逐级恶化的问题,实现ns量级的系统时间同步精度,保证系统各环节在高度统一的时间尺度下进行高效同步与联动工作。通过设计、试验,验证了该方法的可行性和有效性。     

高性能众核处理器芯片时钟网络设计

随着芯片工艺演进与设计规模增加,高性能众核处理器芯片时钟网络设计面临时序和功耗的全方位挑战。为降低芯片时钟网络功耗并缓解时钟网络分布受片上偏差影响导致的时钟偏斜,在H-Tree+MESH混合时钟网络结构的基础上,结合新一代众核处理器芯片面积大及核心时钟网络分布广的特点,基于标准多源时钟树设计策略构建多源时钟树综合（MRCTS）结构,通过全局H-Tree时钟树保证芯片不同区域间时钟偏斜的稳定可控,利用局部时钟树综合进行关键路径的时序优化以实现时序收敛。实验结果表明,MRCTS能在保证时钟延时、时钟偏斜等性能参数可控的基础上,有效降低时钟网络的负载和功耗,大幅压缩综合子模块的布线资源,加速关键路径的时序收敛,并且在相同电源电压和时钟频率的实测条件下,可获得约22.15%的时钟网络功耗优化。     

基于相空间重构与高斯过程的卫星钟差预报

提出了一种基于相空间重构与高斯过程预报卫星钟差的新方法。首先根据星载原子钟的物理特性用多项式进行拟合以提取钟差趋势项,并对拟合后的残差进行经验模态分解,作降噪处理;然后以降噪后的残差时间序列的混沌特性为基础,对其进行相空间重构;最后以重构的相空间为基础,运用高斯过程对残差时间序列进行建模预报,再将预报结果加上趋势项,获得最终的钟差预报值。采用IGS提供的GPS超快速观测钟差建模进行短期预报实验,结果表明,该方法能实时有效地对卫星钟差进行预报,且精度优于超快速预报钟差。     

低功耗高速时钟数据恢复电路

为了降低高速串行接口的时钟数据恢复(CDR)电路的功耗,在研究、分析现有时钟数据恢复结构的基础上,提出了一种新的时钟数据鉴相算法及其电路实现方法。新的电路设计仅使用一个高速采样时钟,比传统的鉴相电路减少一半的采样率,从而减少了前端采样模块的功耗。该鉴相算法采用统计方法减小鉴相时钟的噪声,进而达到很低的误码率。该鉴相算法可使用数字综合的方法实现,工作在较低的频率下,这样便于迁移到不同的工艺中。整个电路使用40nm工艺实现,实际芯片测试数据表明,使用该电路的接收端可以稳定工作在13Gb/s的速率下,功耗达到0.83p J/bit,误码率低于10E-12。