基于滑模控制的 IEEE1588 时钟同步算法研究

针对IEEE1588时钟同步过程中存在时钟频率漂移问题,提出了一种基于滑模控制的新型时钟同步算法。首先根据主从时钟偏差与漂移的递推关系,建立系统状态空间模型;然后运用滑模控制缩小时钟偏差与时钟漂移;最后结合滑动平均滤波对实验过程中的频率抖动和随机误差进行优化。结果表明,基于滑模控制的时钟同步算法可有效抑制时钟漂移引起的时钟偏差线性增长,将时钟偏差控制在1μs以下,从而实现亚微秒级网络对时。相比传统IEEE1588协议同步方法,所提方法提供了更高的同步精度。     

高炉泥炮双向液压锁系统的改进

介绍了石家庄钢铁有限责任公司炼铁厂高炉泥炮使用中出现的振动问题，通过分析高炉泥炮双向液压锁工作原理以及系统的改进，消除了高炉泥炮的振动。     

地下水监测系统电源值更电路的设计与实现

针对地下水监测系统野外工作无人值守、更换电池困难、采样时间短、待机周期长的特点,采用值更电路控制系统在不同功耗状态自动切换的方法延长电源使用寿命。考虑到系统参数配置命令复杂、野外采样情况多样、通信时序不稳定的特性,提出了硬件多触发源与软件状态字配合工作的措施实现系统逻辑控制。引入值更电路的地下水监测系统整体功耗大幅度降低。实测结果验证了值更电路的可行性-表明值更方式必将成为野外监测行业的发展方向。     

一款可综合全数字锁相环设计与分析

全数字锁相环ADPLL拥有较高的集成度、灵活的配置性和快速的工艺可移植性,可以解决模拟电路中无源器件面积过大、抗噪声能力不强、锁定速度慢以及工艺的移植性差等瓶颈问题。在纳米工艺下,单级反相器的最小延时已经达到10ps以内,大大改善了全数字锁相环的抖动性能。提出了一款面向高性能微处理器应用的全数字锁相环结构,并对该结构进行了频域建模和噪声分析。该结构完全采用标准单元设计,最高频率可达到2.4GHz,抖动性能达到ps级别。     

A High-Precision Time Handling Library

An appropriate assessment of end-to-end network performance presumes highly efficient time tracking and measurement with precise time control of the stopping and resuming of program operation. In this paper, a novel approach to solving the problems of highly efficient and precise time measurements on PC-platforms and on ARM-architectures is proposed. A new unified High Performance Timer and a corresponding software library offer a unified interface to the known time counters and automatically identify the fastest and most reliable time source, available in the user space of a computing system. The research is focused on developing an approach of unified time acquisition from the PC hardware and accordingly substituting the common way of getting the time value through Linux system calls. The presented approach provides a much faster means of obtaining the time values with a nanosecond precision than by using conventional means. Moreover, it is capable of handling the sequential time value, precise sleep functions and process resuming. This ability means the reduction of wasting computer resources during the execution of a sleeping process from 100% （busy-wait） to 1-1.5%, whereas the benefits of very accurate process resuming times on long waits are maintained.     

白山发电厂时钟统一对时系统建设

时间同步系统作为智能化水电厂基础支撑系统,在智能化水电厂建设中发挥着基础服务作用。主要介绍了白山发电厂建设对时系统的结构及主要特点,首次采用PTP授时作为备用信号输入,增加了整个时钟系统的稳定性,提高了系统的授时精度,实现远程异地授时。     

机械开关硬件消抖电路设计

通过分析机械开关产生抖动的原因和可能造成的影响,指出了设计机械开关消抖电路的必要性,给出了三种硬件消抖电路的设计方法,电路简单,工作稳定可靠,可在数字电路设计中广泛使用。     

自相似网络的时延抖动性能仿真分析

自相似性对网络性能产生了影响是当前的研究热点。建立了一种基于FBM的自相似网络排队时延抖动分析模型,重点讨论了自相似流量作为输入时对排队系统的时延抖动的影响。对理论分形流量和实际测量流量进行了仿真实验,验证了结果的正确性和有效性。实验结果表明：自相似流量长相关强弱的程度对排队系统时延抖动特性具有非常不同的影响,尤其是在缓存较大的情况下。同时,还发现网络流量中长相关发生作用时状态转变与排队系统本身的参数也有关,这是新的发现,对实时业务的网络性能评价具有重要的参考意义。     

基于LFSR的钟控密钥流生成器

本文提出了一种基于LFSR的钟控密钥流生成器。该生成器通过一个钟控线性移位寄存器从15个级数是两两互素的线性移位寄存器中控制选取10个,将所选出的各线性移位寄存器生成的m序列相加,然后输出,从而达到了伪随机序列周期扩大的目的。本文还对密钥流生成器的线性复杂度、均匀性、相关性以及游程特性进行了分析。分析表明,该生成器生成序列的周期能达到2128,而且有较大的线性复杂度和良好的相关性和均匀性。认为该序列可以作为密钥流序列进行加密。通过钟控的方式随机选取用于相加的m序列,增加了密钥流序列的条数。此外,本文还给出了该生成器的具体实现算法,有一定的实用价值。     

Influence of wall charge distribution on time lag of address discharge in AC plasma display panels

The influence of wall charge distribution on the time lag of address discharge in an AC plasma display panel is investigated using two different reset waveforms: one (typical reset) induces both face and surface discharges and the other (TR reset) induces face discharges only. The measured formative time lag and statistical time lag of address discharge for TR were 21–31 ns and 31–74 ns shorter than the one for the typical reset, respectively. The TR reset resulted in much less increase of statistical time lag than the typical reset when the reset-to-address time interval was increased, and 70 ns smaller deviation of the statistical time lag among different color cells. Calculations show that the TR reset forms a much smoother wall charge profile, which is less susceptible to cell parameter variations, than the typical reset. The observed differences in the time lags of address discharge between different scan lines and color cells are strongly correlated to the differences of the wall charge profile, indicating that a smooth wall charge profile formed by the reset using face discharges only reduces the time lag of address discharge and minimizes the susceptibility of address discharge to cell parameter variation.